74ALVCH16374 View Datasheet(PDF) - ON Semiconductor

Part Name

Description

Manufacturer

74ALVCH16374

Low−Voltage 16−Bit D−Type Flip−Flop with Bus Hold 1.8/2.5/3.3 V(3−State, Non−Inverting)

ON Semiconductor 

74ALVCH16374

Low−Voltage 16−Bit D−Type

Flip−Flop with Bus Hold

1.8/2.5/3.3 V

(3−State, Non−Inverting)

The 74ALVCH16374 is an advanced performance, non−inverting

16−bit D−type flip−flop. It is designed for very high−speed, very

low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The

VCXH16374 is byte controlled, with each byte functioning

identically, but independently. Each byte has separate Output Enable

and Clock Pulse inputs. These control pins can be tied together for full

16−bit operation.

The 74ALVCH16374 consists of 16 edge−triggered flip−flops with

individual D−type inputs and 3.6 V−tolerant 3−state outputs. The

clocks (CPn) and Output Enables (OEn) are common to all flip−flops

within the respective byte. The flip−flops will store the state of

individual D inputs that meet the setup and hold time requirements on

the LOW−to−HIGH Clock (CP) transition. With the OE LOW, the

contents of the flip−flops are available at the outputs. When the OE is

HIGH, the outputs go to the high impedance state. The OE input level

does not affect the operation of the flip−flops. The data inputs include

active bushold circuitry, eliminating the need for external pull−up

resistors to hold unused or floating inputs at a valid logic state.

• Designed for Low Voltage Operation: VCC = 1.65 − 3.6 V

• 3.6 V Tolerant Inputs and Outputs

• High Speed Operation: 3.6 ns max for 3.0 to 3.6 V

4.5 ns max for 2.3 to 2.7 V

7.8 ns max for 1.65 to 1.95 V

• Static Drive: ±24 mA Drive at 3.0 V

±12 mA Drive at 2.3 V

±4 mA Drive at 1.65 V

• Supports Live Insertion and Withdrawal

• Includes Active Bushold to Hold Unused or Floating Inputs at a Valid

Logic State

• IOFF Specification Guarantees High Impedance When VCC = 0 V†

• Near Zero Static Supply Current in All Three Logic States (40 mA)

Substantially Reduces System Power Requirements

• Latchup Performance Exceeds ±250 mA @ 125°C

• ESD Performance: Human Body Model >2000V; Machine Model >200V

• Second Source to Industry Standard 74ALVCH16374

http://onsemi.com

MARKING DIAGRAM

48

48

1

TSSOP−48

DT SUFFIX

CASE 1201

74ALVCH16374DT

AWLYYWW

1

A

= Assembly

Location

WL

= Wafer Lot

YY

= Year

WW

= Work Week

PIN NAMES

Pins

Function

OEn

CPn

D0−D15

O0−O15

Output Enable Inputs

Clock Pulse Inputs

Inputs

Outputs

ORDERING INFORMATION

Device

Package

74ALVCH16374DTR

TSSOP

Shipping

2500 / Reel

†To ensure the outputs activate in the 3−state condition, the output enable pins

should be connected to VCC through a pull−up resistor. The value of the resistor is

determined by the current sinking capability of the output connected to the OE pin.

© Semiconductor Components Industries, LLC, 2006

1

June, 2006 − Rev. 3

Publication Order Number:

74ALVCH16374/D

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