8 (14)
4 (7)
2 (3)
R2
1 (1)
2N2907
C
R1
VCC
7 (12)
SG1842/43
5 (9)
7 (11)
6 (10)
5 (8)
3 (5)
Typical Application Circuits
VIN
Q1
I
RS
Figure 21 · Adjustable Buffered Reduction of Clamp Level with Softstart
IPK
=
VCS
RS
Where, VCS=1.67 �R1R+1R2� and VC.S.MAX = 1V (Typ.)
tSOFTSTART
=
−ln
�1
−
VEAO
5 �R1
−
R1
+
1.3
�
R2�
�RR1 1+RR2 2� C
Where, VEAO ≡ voltage at the Error Amp Output under minimum line and maximum load conditions
Softstart and adjustable peak current can be done with the external circuitry shown above.
8 (14)
RA
8
4
6
555
3
RB
TIMER
4 (7)
SG1842/43
2
C
1
5 (9)
f=
1.44
(RA + 2RB) C
f=
RB
RA + 2RB
To other
SG1842/43
Figure 22 · External Duty Cycle Clamp and Multi-Unit Synchronization
Precision duty cycle limiting as well as synchronizing several 1842/1843's is possible with the above
circuitry.
15