NXP Semiconductors
74HC7403; 74HCT7403
4-bit x 64-word FIFO register; 3-state
19. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
8
9
10
11
12
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
12.10
12.11
12.12
13
13.1
13.1.1
13.1.2
13.1.3
13.1.4
13.1.5
13.1.6
14
15
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Expanded format . . . . . . . . . . . . . . . . . . . . . . . 5
Parallel expension . . . . . . . . . . . . . . . . . . . . . . 5
Serial expension . . . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Shifting in sequence FIFO empty to FIFO full. 13
With FIFO full; SI held HIGH in anticipation
of empty location . . . . . . . . . . . . . . . . . . . . . . 14
Master reset applied with FIFO full . . . . . . . . . 15
SO input to DOR output propagation delay . . 16
With FIFO empty; SO is held HIGH in
anticipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Shift-in operation; high speed burst mode . . . 17
Shift-out operation; high speed burst mode . . 18
Set-up and hold times. . . . . . . . . . . . . . . . . . . 18
SO input to Qn outputs propagation delay . . . 19
MR to SI recovery time . . . . . . . . . . . . . . . . . . 19
Enable and disable times . . . . . . . . . . . . . . . . 20
Test circuit for measuring switching times . . . 21
Application information. . . . . . . . . . . . . . . . . . 22
Expanded format . . . . . . . . . . . . . . . . . . . . . . 23
Sequence 1 (both FIFOs empty,
starting SHIFT-IN process) . . . . . . . . . . . . . . . 27
Sequence 2 (FIFOB runs full) . . . . . . . . . . . . . 27
Sequence 3 (FIFOA runs full) . . . . . . . . . . . . . 28
Sequence 4 (both FIFOs full, s
tarting SHIFT-OUT). . . . . . . . . . . . . . . . . . . . . 28
Sequence 5 (FIFOA runs empty) . . . . . . . . . . 28
Sequence 6 (FIFOB runs empty) . . . . . . . . . . 28
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 29
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 31
Legal information. . . . . . . . . . . . . . . . . . . . . . . 32
17.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 32
17.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
17.3
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 32
17.4
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 33
18
Contact information . . . . . . . . . . . . . . . . . . . . 33
19
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 24 September 2012
Document identifier: 74HC_HCT7403