Nexperia
74ALVCH16843
18-bit bus-interface D-type latch; 3-State
VI 90 %
tW
negative
pulse
VM
10 %
0V
tf
VI
positive
pulse
tr
90 %
VM
10 %
0V
tW
VM
tr
tf
VM
VCC
VI
PULSE
GENERATOR
VO
DUT
RT
VEXT
RL
CL
RL
001aae235
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistance;
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to output impedance Zo of the pulse generator;
VEXT = External voltage for measuring switching times.
Figure 11. Test circuit for measuring switching times
Table 9. Test data
Input
VCC
2.3 V to 2.7 V
2.7 V
VI
VCC
2.7 V
3.0 V to 3.6 V
2.7 V
tr, tf
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
Load
RL
500 Ω
500 Ω
500 Ω
CL
30 pF
50 pF
50 pF
VEXT
tPHZ, tPZH
GND
GND
GND
tPLZ, tPZL
2 × VCC
2 × VCC
2 × VCC
tPLH, tPHL
open
open
open
74ALVCH16843
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 20 November 2017
© Nexperia B.V. 2017. All rights reserved.
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