AD5301 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD5301 Datasheet PDF : 16 Pages
| |||
AD5301/AD5311/AD5321
PIN CONFIGURATIONS
6-Lead SOT-23
(RT-6)
8-Lead MSOP
(RM-8)
GND 1 AD5301/ 6 VDD
SDA 2
AD5311/
AD5321
5 A0
SCL 3 TOP VIEW 4 VOUT
(Not to Scale)
VDD 1
A0 2
A1 3
AD5301/
AD5311/
AD5321
8 GND
7 SDA
6 SCL
VOUT
4
TOP VIEW
(Not to Scale)
5
PD
MSOP
Pin No.
1
2
3
4
5
6
7
8
PIN FUNCTION DESCRIPTION
SOT-23
Pin No.
6
5
N/A
4
N/A
3
2
1
Mnemonic
VDD
A0
A1
VOUT
PD
SCL
SDA
GND
Function
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply
should be decoupled with a 10 µF in parallel with a 0.1 µF capacitor to GND.
Address Input. Sets the least significant bit of the 7-bit slave address.
Address Input. Sets the second least significant bit of the 7-bit slave address.
Buffered Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
Active Low Control Input that Acts as a Hardware Power-Down Option. This pin overrides any
software power-down option. The DAC output goes three-state and the current consumption
of the part drops to 50 nA @ 3 V (200 nA @ 5 V).
Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 16-bit
input shift register. Clock rates of up to 400 kbit/s can be accommodated in the I2C compat-
ible interface. SCL may be CMOS/TTL driven.
Serial Data Line. This is used in conjunction with the SCL line to clock data into the 16-bit
input shift register during the write cycle and to read back one or two bytes of data
(one byte for the AD5301, two bytes for the AD5311/AD5321) during the read cycle. It is
a bidirectional open-drain data line that should be pulled to the supply with an external
pull-up resistor. If not used in readback mode, SDA may be CMOS/TTL driven.
Ground Reference Point for All Circuitry on the Part.
REV. A
–5–
Share Link: 