Philips Semiconductors
N-channel enhancement mode vertical
D-MOS transistor
CHARACTERISTICS
Tj = 25 °C unless otherwise specified
Drain-source breakdown voltage
ID = 100 µA; VGS = 0
Drain-source leakage current
VDS = 160 V; VGS = 0
Gate-source leakage current
VGS = 20 V; VDS = 0
Gate threshold voltage
ID = 1 mA; VDS = VGS
Drain-source ON-resistance
ID = 250 mA; VGS = 10 V
Transfer admittance
ID = 250 mA; VDS = 15 V
Input capacitance at f = 1 MHz
VDS = 10 V; VGS = 0
Output capacitance at f = 1 MHz
VDS = 10 V; VGS = 0
Feedback capacitance at f = 1 MHz
VDS = 10 V; VGS = 0
Switching times (see Figs 2 and 3)
ID = 250 mA; VDD = 50 V; VGS = 0 to 10 V
V(BR)DSS
IDSS
IGSS
VGS(th)
RDS(on)
Yfs
Ciss
Coss
Crss
ton
toff
Product specification
BST84
min. 200 V
max.
10 µA
max.
min.
max.
100 nA
0.8 V
2.8 V
typ.
max.
6Ω
12 Ω
typ.
250 mS
typ.
max.
70 pF
90 pF
typ.
max.
20 pF
30 pF
typ.
max.
typ.
max.
typ.
max.
5 pF
10 pF
4 ns
10 ns
15 ns
25 ns
April 1995
4