AD9117BCPZRL7 View Datasheet(PDF) - Analog Devices
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Description
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AD9117BCPZRL7 Datasheet PDF : 52 Pages
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Data Sheet
REVISION HISTORY
12/2017—Rev. C to Rev. D
Changes to Figure 94 ......................................................................41
Changes to Estimating the Overall DAC Pipeline Delay Section ..42
Updated Outline Dimensions........................................................51
Changes to Ordering Guide...........................................................52
3/2013—Rev. B to Rev. C
Change to Features Section..............................................................1
Change to Endnote 1, Table 1 ..........................................................6
Changes to Figure 86 and Figure 88 .............................................34
Change to Table 13 ..........................................................................35
Change to Version Register Description, Table 14 .....................39
Changes to Table 17 and Reference Control Amplifier
Section ..............................................................................................43
Changes to Using the Internal Termination Resistors
Section ..............................................................................................46
Changes to Single-Ended Buffered Output Using an Op Amp
Section ..............................................................................................47
Changes to Differential Buffered Output Using an Op Amp
Section ..............................................................................................48
Updated Outline Dimensions........................................................51
5/2012—Rev. A to Rev. B
Changes to Table 1 ............................................................................5
Changes to Table 2 ............................................................................7
Changes to Table 3 and Table 4 .......................................................8
Changes to Theory of Operation Section ....................................32
Changes to SCLK—Serial Clock Section .....................................33
Changes to Pin Mode Section........................................................34
Changes to Table 14 ........................................................................37
Changes to Self-Calibration Section.............................................44
Deleted Modifying the Evaluation Board to Use the ADL5370
On-Board Quadrature Modulator Section.......................................... 51
Deleted Evaluation Board Schematics and Artwork Section and
Figure 111 to Figure 133, Renumbered Sequentially..................52
Updated Outline Dimensions........................................................51
Changes to Ordering Guide...........................................................52
Deleted Bill of Materials Section and Table 18............................75
AD9114/AD9115/AD9116/AD9117
3/2009—Rev. 0 to Rev. A
Changes to Product Title and General Description Section .......1
Changes to Figure 1 .......................................................................... 4
Changed IOUTFS = 2 mA to IxOUTFS = 20 mA .................................... 5
Changes to Table 1 ............................................................................ 6
Changed IOUTFS = 2 mA to IxOUTFS = 20 mA .................................... 7
Changes to Table 2 ............................................................................ 7
Changed DVDDIO = 1.8 V to DVDDIO = 3.3 V, Table 3 and
CVDD = 3.3 V to CVDD = 1.8 V, Table 4 ..................................... 8
Changes to Table 5 and Table 6 ....................................................... 9
Changes to Table 7 ..........................................................................10
Changes to Table 8 ..........................................................................12
Changes to Table 9 ..........................................................................14
Changes to Table 10 ........................................................................16
Changes to Typical Performance Characteristics Section .........18
Changes to Theory of Operation Section and Figure 84 ...........32
Added Figure 85 to Figure 88; Renumbered Sequentially.........34
Changes to Table 13 ........................................................................35
Changes to Table 14 ........................................................................36
Changes to Digital Interface Operation Section and Figure 89,
Figure 90, Figure 91, Figure 92, and Figure 93............................40
Changes to Figure 94, Digital Data Latching Section, and
Retimer Section ...............................................................................41
Added Reference Operation Section, Reference Control
Amplifier Section, DAC Transfer Function Section, Figure 96,
and Table 17 .....................................................................................43
Added Analog Output Section ......................................................44
Changes to Auxiliary DACs Section.............................................48
Changes to DAC to Modulator Interfacing Section, Figure 107,
and Figure 108 .................................................................................49
Added Figure 111 to Figure 133....................................................52
Added Table 18 ................................................................................75
8/2008—Revision 0: Initial Version
Rev. D | Page 3 of 52
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