LS7212-S View Datasheet(PDF) - LSI Corporation

Part Name

Description

Manufacturer

LS7212-S

No description available.

LSI Corporation  

t0

Clock

TRIG

A,B

t3

WB0-WB7

OUT

t1

t2

A = 0, B = 1, Delayed Operate

Programmed Delay

t1

t4

t4

Immediate Release

Note 1. TRIG input is clocked in by the negative edge of external clock.

Note 2. Inputs A, B and WB0 - WB7 are sampled only at a TRIG input transition and ignored at all other times.

Note 3. OUT is switched by the positive edge of the external clock.

FIGURE 3. INPUT/OUTPUT TIMING

TRIG

RESET

OUT(OS)

OUT(DO)

OUT(DR)

OUT(DD)

A

B

C

D

E

F

G

H

A. Turn-on delay in DO and DD modes; Pulse-width in OS mode.

B. Turn-off delay in DR and DD modes.

C. Pulse-width extended by re-trigger in OS mode. No effect in DO and DD modes because TRIG switches back low

before turn-on delay has timed out.

D. Turn-off delay in DR mode.

E. Turn-on delay in DO and DD modes; pulse-width in OS mode.

F. No effect in DO, DR and DD modes because of TRIG’s switching back to opposite levels.

G. Time-outs aborted and OUT force high by RESET.

H. After the removal of RESET, OUT switches to the inverse polarity of TRIG immediately (DR) or after the timeout

(DO,DD). No effect in OS.

FIGURE 4. MODE ILLUSTRATION WITH TRIG, OUT AND RESET

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