FAN6751HLMY View Datasheet(PDF) - Fairchild Semiconductor

Part Name

Description

Manufacturer

FAN6751HLMY

Highly Integrated Green-Mode PWM Controller

Fairchild Semiconductor 

AN-6073

APPLICATION NOTE

Internal Block Operation

Startup and Soft-Start Circuitry

When power is turned on, the internal high-voltage startup

current (typically 2mA) charges the hold-up capacitor C1

through startup resistor RHV. RHV can be directly connected

by VBULK to the HV pin. The built-in 5ms soft-start circuit

starts when the VDD pin reaches the start threshold voltage

VDD-ON. Soft-start helps reduce the inrush current, the startup

current spike, and output voltage overshoot during the

startup period, as shown in Figure 4. When VDD reaches

VDD-ON, the internal high-voltage startup current is switched

off and the supply current is drawn from the auxiliary

winding of the main transformer, as shown in Figure 5.

VDD

SQ

R

Soft

Driver

Soft Start

8 GATE

6 Sense

Figure 4. Soft-start Circuit

Figure 6. UVLO Specification

Under-Voltage Lockout (UVLO)

The FAN6751 has a voltage detector on the VDD pin to

ensure that the chip has enough power to drive the

MOSFET. Figure 7 shows a hysteresis of the turn-on and

turn-off threshold levels and an open-loop-release voltage.

Figure 5. Startup Circuit for Power Transfer

Figure 7. UVLO Specification

If a shorter startup time is required, a two-step startup

circuit, as shown Figure 6, is recommended. In this circuit, a

smaller capacitor C1 can be used to reduce startup time. The

energy supporting the FAN6751 after startup is mainly from

a larger capacitor C2. If a shorter releasing latch mode time

is required, a DHV and RHV can be directly connected by VAC

to the HV pin.

The turn-on and turn-off thresholds are internally fixed at

16.5V and 10.5V. During startup, the VDD’s capacitor must

be charged to 16.5V to enable the IC. The capacitor

continues to supply the VDD until the energy can be

delivered from the auxiliary winding of the main

transformer. The VDD must not drop below 10.5V during the

startup sequence.

When the supply current is drawn from the transformer, it

draws a leakage current of about 1µA from HV pin. The

maximum power dissipation of the RHV is:

PRHV = IHV − LC(Typ.)2 × RHV

= IμA2 ×100KΩ ≅ 0.1μW

(1)

where

IHV-LC is the supply current drawn from HV pin, and

RHV is 100KΩ.

To further limit the input power under a short-circuit or

open-loop condition, a special two-step UVLO mechanism

prolongs the discharge time of the VDD capacitor. Figure 8

shows the traditional UVLO method along with the special

two-step UVLO method. In the two-step UVLO mechanism,

an internal sinking current, IDD-OLP, pulls the VDD voltage

toward the VDD-OLP. This sinking current is disabled after the

VDD drops below VDD-OLP; after which, the VDD voltage is

again charged towards VDD-ON. With the addition of the two-

step UVLO mechanism, the average input power during a

short-circuit or open-loop condition is greatly reduced. As a

result, over-heating does not occur.

© 2008 Fairchild Semiconductor Corporation

Rev. 1.0.0 • 9/26/08

3

www.fairchildsemi.com

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