HI5960IB View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
HI5960IB Datasheet PDF : 12 Pages
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HI5960
Timing Diagrams
CLK
50%
D13-D0
IOUT
ERROR BAND
tSETT
tPD
FIGURE 2. OUTPUT SETTLING TIME DIAGRAM
V
GLITCH AREA = 1/2 (H x W)
HEIGHT (H)
WIDTH (W)
t (ps)
FIGURE 3. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
CLK
D13-D0
IOUT
tPW1
tPW2
tSU
tSU
tSU
tHLD
tHLD
tHLD
tPD
tSETT
50%
tPD
tSETT
tPD
tSETT
FIGURE 4. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
FN4655 Rev 6.00
March 31, 2005
Page 10 of 12
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