Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
Timing Diagrams (continued)
NOTE: SEE FIGURE 4 FOR WR AND LATCH TIMING.
DATA (N)
DATA (N + 1)
DATA (N + 2)
WR
LATCH
1st-RANK REGISTER DATA
2nd-RANK REGISTER DATA
(EDGE/LEVEL = GND)
2nd-RANK REGISTER DATA
(EDGE/LEVEL = VCC)
DATA (N)
DATA (N + 1)
DATA (N + 2)
DATA (N)
DATA (N + 1)
DATA (N)
DATA (N + 1)
Figure 5. Parallel-Interface Mode Format (SER/PAR = GND)
NOTES: SEE TABLE 2 FOR INPUT DATA.
SEE FIGURE 4 FOR WR AND LATCH TIMING.
INPUT DATA FOR OUT0
INPUT DATA FOR OUT1 TO OUT6
INPUT DATA FOR OUT7
0D3
0D2
0D1
0D0
1D3
1D2
7D3
7D2
7D1
7D0
WR
LATCH
2nd-RANK REGISTER DATA
(EDGE/LEVEL = GND)
2nd-RANK REGISTER DATA
(EDGE/LEVEL = VCC)
Figure 6. Serial-Mode Interface Format (SER/PAR = VCC)
DATA VALID
DATA VALID
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