SDRAM (Rev.1.31)
Single Data Rate
Apr. '02
MITSUBISHI LSIs
M2V56S20/ 30/ 40 ATP
M2V56S20/ 30/ 40 AKT
256M Synchronous DRAM
[ Write with Auto-Precharge Interrupted by Write / Read to Different Bank ]
Burst write with auto-precharge can be interrupted by write or read to different bank. Next ACT
command can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-precharge interruption by a
command to the same bank is inhibited.
WRITEA Interrupted by WRITE to Different Bank (BL=4)
CLK
Command
Write
Write
BL
A0-9,11-12
Ya
Yb
tWR
A10
1
0
ACT
tRP
Xa
Xa
BA0-1
00
10
00
DQ
Da0 Da1 Db0 Db1 Db2 Db3
auto-precharge interrupted
precharge
activate
WRITEA Interrupted by READ to Different Bank (CL=2, BL=4)
CLK
Command
Write
Read
BL
A0-9,11-12
Ya
Yb
tWR
A10
1
0
ACT
tRP
Xa
Xa
BA0-1
00
10
00
DQ
Da0 Da1
Qb0 Qb1 Qb2 Qb3
auto-precharge interrupted
precharge
activate
MITSUBISHI ELECTRIC
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