Function Tables
Table 3A. Clock Select Function Table
Control Input
Clock
CLK_SEL
PCLK, nPCLK
LVCMOS_CLK
0
Selected
De-selected
1
De-selected
Selected
ICS83940DI Datasheet
Table 3B. Clock Input Function Table
Inputs
CLK_SEL LVCMOS_CLK
PCLK
0
–
0
0
–
1
0
–
0
0
–
1
0
–
Biased; NOTE
1
0
–
Biased; NOTE
1
1
0
–
1
1
–
nPCLK
1
0
Biased; NOTE
1
Biased; NOTE
1
0
1
–
–
Outputs
Q[0:17]
LOW
HIGH
Input to Output Mode
Differential to Single-Ended
Differential to Single-Ended
LOW Single-Ended to Single-Ended
HIGH Single-Ended to Single-Ended
HIGH Single-Ended to Single-Ended
LOW
LOW
HIGH
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
Non-Inverting
Non-Inverting
NOTE 1: Please refer to the Application Information Section, Wiring the Differential Input to Accept Single-ended Levels.
©2020 Renesas Electronics Corporation
3
January 7, 2020