DS1848E-050TR View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
DS1848E-050TR Datasheet PDF : 17 Pages
| |||
DS1848
NOTES:
1) All voltages are referenced to ground.
2) Inputs SDA = SCL = WP = Vcc. A0, A1, and A2 must be tied to VCC or GND.
3) Valid at 25°C only.
4) Absolute linearity is the difference of measured value from expected value at DAC position.
Expected value is a straight line from measured minimum position to measured maximum position.
5) Relative linearity the deviation of an LSB DAC setting change vs. the expected LSB change.
Expected LSB change is the slope of the straight line from measured minimum position to measured
maximum position.
6) A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line tRMAX + tSU:DAT = 1000ns + 250ns = 1250ns before the SCL line is released.
7) After this period, the first clock pulse is generated.
8) The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL signal.
9) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
VIH MIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
10) CB — total capacitance of one bus line in picofarads, timing referenced to 0.9VCC and 0.1VCC.
11) EEPROM write begins after a stop condition occurs.
12) The temperature coefficient varies with resistor position from 650ppm/°C at position FFh to
1000ppm/°C at 00h (for the 50k resistor), or 1500ppm/°C at 00h (for the 10k resistor). See the graphs
below. The tempco can be significantly reduced by using the resistor calibration values. When doing
so, the average tempco over the entire temperature range is between 200ppm/°C (for the lower
positions) and 10ppm/°C (higher positions). Refer to the Programming the Look-Up Table section of
the data sheet.
13) I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VCC is switched off.
14) Refer to Programming the Look-Up Table section of the data sheet for calibration.
15) Address input A1 passes Latch-up per JEDEC 78 class I. All other pins pass class II.
TEMPCO vs. RESISTANCE
10K RESISTOR
1500
1400
1300
1200
1100
1000
900
800
700
600
500
0
2000 4000 6000 8000 10000
RESISTANCE (OHMS)
ORDERING INFORMATION
ORDERING
PACKAGE
TEMPCO vs. RESISTANCE
50K RESISTOR
1100
1000
900
800
700
600
500
0
10000 20000 30000 40000 50000
RESISTANCE (OHMS)
OPERATING
16 of 17
VERSION
Share Link: 