PEB 2447
Overview
1.5 Pin Definitions and Functions (cont’d)
Pin No.
16
17
18
19
20
21
26
25
24
23
22
27
Symbol
FS0
FS1
FS2
FS3
FS4
FS5
A0
A1
A2
A3
A4
CS
Input (I)
Output (O)
Tristate (T)
I
I
I
I
I
I
I
I
I
I
I
I
28
RES
I
29
WR
I
30
RD
I
31
SP
I
39
D0
I/O/T
38
D1
I/O/T
37
D2
I/O/T
36
D3
I/O/T
35
D4
I/O/T
34
D5
I/O/T
33
D6
I/O/T
32
D7
I/O/T
Function
Frame Measuring Inputs: These inputs are used
as frame evaluation inputs.
Address Bus Bit 0 to 4: These inputs interface to
the systems address bus to select an internal
register for a read or write access.
Chip Select: (low active) A low level selects the
MTSXL for a register access operation.
Reset: A high signal on this Input forces the MTSXL
into reset state.
Write: (low active) This signal indicates a write
operation.
Read: (low active) This signal indicates a read
operation.
Synchronization Pulse: The MTSXL is
synchronized to the PCM system via this line.
Data Bus: These pins transfer data between the µP
and the MTSXL.
Semiconductor Group
8
03.97