ISL22317TFRTZ View Datasheet(PDF) - Renesas Electronics

Part Name

Description

Manufacturer

ISL22317TFRTZ

Precision Single Digitally Controlled Potentiometer (XDCP™) Low Noise, Low Power, I2C™ Bus, 128 Taps

Renesas Electronics 

ISL22317

precision DCP by setting this bit to 1. Default value of the

Precision Off bit is 0, i.e. matching to external resistor is ON.

Note, if the external resistor between REF_A/REF_B is not

populated, the DCP will work as a normal DCP without giving

99% precision and with ~40% higher value of the resistance. It

is highly recommended to use the bit option (MSR<6>) to turn

OFF the precision mode first and then removing the external

resistor.

All other bits MSR<5:0> are reserved and cannot be written.

Any value read from these bits should be ignored.

I2C Serial Interface

The ISL22317 supports an I2C bi-directional bus oriented

protocol. The protocol defines any device that sends data onto

the bus as a transmitter and the receiving device as the

receiver. The device controlling the transfer is a master and the

device being controlled is the slave. The master always

initiates data transfers and provides the clock for both transmit

and receive operations. Therefore, the ISL22317 operates as a

slave device in all applications.

All communication over the I2C interface is conducted by

sending the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line must change only during SCL

LOW periods. SDA state changes during SCL HIGH are

reserved for indicating START and STOP conditions (see

Figure 21). On power-up of the ISL22317, the SDA pin is in the

input mode.

All I2C interface operations must begin with a START

condition, which is a HIGH to LOW transition of SDA while SCL

is HIGH. The ISL22317 continuously monitors the SDA and

SCL lines for the START condition and does not respond to

any command until this condition is met (see Figure 21). A

START condition is ignored during the power-up of the device.

All I2C interface operations must be terminated by a STOP

condition, which is a LOW to HIGH transition of SDA while SCL

is HIGH (see Figure 21). A STOP condition at the end of a read

operation, or at the end of a write operation, places the device

in its standby mode.

An ACK, Acknowledge, is a software convention used to

indicate a successful data transfer. The transmitting device,

either master or slave, releases the SDA bus after transmitting

eight bits. During the ninth clock cycle, the receiver pulls the

SDA line LOW to acknowledge the reception of the eight bits of

data (see Figure 22).

The ISL22317 responds with an ACK after recognition of a

START condition followed by a valid Identification Byte, and

once again after successful receipt of an Address Byte. The

ISL22317 also responds with an ACK after receiving a Data

Byte of a write operation. The master must respond with an

ACK after receiving a Data Byte of a read operation

A valid Identification Byte contains 01010 as the five MSBs,

and the following bit matching the logic value present at pin A1.

The LSB is the Read/Write bit. Its value is “1” for a Read

operation, and “0” for a Write operation (See Table 4).

TABLE 4. IDENTIFICATION BYTE FORMAT

Logic value at pin A1

0

1

0

1

0

A1

0

R/W

(MSB)

(LSB)

SCL

SDA

START

DATA

DATA

DATA

STABLE CHANGE STABLE

STOP

FIGURE 21. VALID DATA CHANGES, START, AND STOP CONDITIONS

FN6912 Rev 1.00

April 15, 2010

Page 12 of 15

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