ISL6251HRZ View Datasheet(PDF) - Renesas Electronics

Part Name

Description

Manufacturer

ISL6251HRZ

Low Cost Multi-Chemistry Battery Charger Controller

Renesas Electronics 

ISL6251, ISL6251A

iˆin

iˆL L

vˆ o

vˆ in

+

ILdˆ 1:D Vindˆ

RT

Rc

Ro

VCA2

Co

Ti(S)

dˆ

K

11/Vin

0.25VCA2

+

-

Tv(S)

vˆcomp -Av(S)

FIGURE 14. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK

REGULATOR

Figure 15 shows the voltage loop compensator, and its transfer

function is expressed as follows:

Av

S



vˆ comp

vˆ FB

1 S

 gm

 cz

SC1

(EQ. 25)

where

 cz



1

R1C1

Vo

VFB -

VREF + gm

VCOMP

R1

C1

FIGURE 15. VOLTAGE LOOP COMPENSATOR

Compensator design goal:

• High DC gain

•

Loop bandwidth fc:

 1

5



1

20





fs

• Gain margin: >10dB

• Phase margin: 40°

The compensator design procedure is as follows:

1. Put compensator zero at:

cz



1  3 1

RoCo

(EQ. 26)

2. Put one compensator pole at zero frequency to achieve high

DC gain, and put another compensator pole at either ESR zero

frequency or half switching frequency, whichever is lower.

The loop gain Tv(S) at cross over frequency of fc has unity gain.

Therefore, the compensator resistance R1 is determined by

Equation 27:

R1 = 8--------f--Cg----mV----O-V----FC----B-O----R-----T-

(EQ. 27)

where gm is the trans-conductance of the voltage loop error

amplifier. Compensator capacitor C1 is then given by

Equation 28:

C1



1

R1 cz

(EQ. 28)

Example: Vin = 19V, Vo = 16.8V, Io = 2.6A, fs = 300kHz,

Co = 10F/10m, L = 10H, gm = 250s, RT = 0.8,

VFB = 2.1V, fc = 20kHz, then compensator resistance R1 = 10k.

Choose R1 = 10k. Put the compensator zero at 1.5kHz. The

compensator capacitor is C1 = 6.5nF. Therefore, choose voltage

loop compensator: R1 = 10k, C1 = 6.5nF.

PCB Layout Considerations

Power and Signal Layers Placement on the

PCB

As a general rule, power layers should be close together, either

on the top or bottom of the board, with signal layers on the

opposite side of the board. As an example, layer arrangement on

a 4-layer board is shown below:

1. Top Layer: signal lines, or half board for signal lines and the

other half board for power lines

2. Signal Ground

3. Power Layers: Power Ground

4. Bottom Layer: Power MOSFET, Inductors and other Power

traces

Separate the power voltage and current flowing path from the

control and logic level signal path. The controller IC will stay on

the signal layer, which is isolated by the signal ground to the

power signal traces.

Component Placement

The power MOSFET should be close to the IC so that the gate

drive signal, the LGATE, UGATE, PHASE, and BOOT, traces can be

short.

Place the components in such a way that the area under the IC

has less noise traces with high dv/dt and di/dt, such as gate

signals and phase node signals.

Signal Ground and Power Ground

Connection.

At minimum, a reasonably large area of copper, which will shield

other noise couplings through the IC, should be used as signal

ground beneath the IC. The best tie-point between the signal

ground and the power ground is at the negative side of the output

capacitor on each side, where there is little noise; a noisy trace

beneath the IC is not recommended.

FN9202 Rev 3.00

March 13, 2014

Page 17 of 20

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