P89LPC915 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

P89LPC915

8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V flash with 8-bit A/D converter

NXP Semiconductors. 

NXP Semiconductors

P89LPC915/916/917

8-bit microcontrollers with accelerated two-clock 80C51 core

Table 5. P89LPC916 pin description …continued

Symbol

Pin

Type Description

I

RST — External Reset input during power-on or if selected via UCFG1.

When functioning as a reset input, a LOW on this pin resets the

microcontroller, causing I/O ports and peripherals to take on their

default states, and the processor begins execution at address 0. Also

used during a power-on sequence to force ISP mode. When using an

oscillator frequency above 12 MHz, the reset input function of P1.5

must be enabled. An external circuit is required to hold the device

in reset at power-up until VDD has reached its specified level. When

system power is removed VDD will fall below the minimum

specified operating voltage. When using an oscillator frequency

above 12 MHz, in some applications, an external brownout detect

circuit may be required to hold the device in reset when VDD falls

below the minimum specified operating voltage.

P2.2 to P2.5

Port 2: Port 2 is a 4-bit I/O port with a user-configurable output type.

During reset Port 2 latches are configured in the input only mode with

the internal pull-up disabled. The operation of Port 2 pins as inputs and

outputs depends upon the port configuration selected. Each port pin is

configured independently. Refer to Section 8.13.1 “Port configurations”

and Table 15 “Static characteristics” for details.

All pins have Schmitt triggered inputs.

Port 2 also provides various special functions as described below:

P2.2/MOSI

6

I/O P2.2 — Port 2 bit 2.

I/O MOSI — SPI master out slave in. When configured as master, this pin is

output; when configured as slave, this pin is input.

P2.3/MISO

5

I/O P2.3 — Port 2 bit 3.

I/O MISO — When configured as master, this pin is input, when configured

as slave, this pin is output.

P2.4/SS

2

I/O P2.4 — Port 2 bit 4.

I/O SS — SPI Slave select.

P2.5/SPICLK

11

I/O P2.5 — Port 2 bit 5.

I/O SPICLK — SPI clock. When configured as master, this pin is output;

when configured as slave, this pin is input.

VSS

4

I

Ground: 0 V reference.

VDD

12

I

Power supply: This is the power supply voltage for normal operation as

well as Idle and Power-down modes.

[1] Input/output for P1.0 to P1.3. Input for P1.5.

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

© NXP B.V. 2009. All rights reserved.

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