CY7C1440AV33-167BZXC(2005) View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

CY7C1440AV33-167BZXC
(Rev.:2005)

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

Cypress Semiconductor 

PRELIMINARY

CY7C1440AV33

CY7C1442AV33

CY7C1446AV33

Logic Block Diagram – CY7C1440AV33 (1 Mbit x 36)

A0, A1, A

MODE

ADDRESS

REGISTER

2

A[1:0]

ADV

CLK

ADSC

ADSP

BWD

BWC

BWB

BWA

BWE

GW

CE1

CE2

CE3

OE

DQD ,DQPD

BYTE

WRITE REGISTER

DQC ,DQPC

BYTE

WRITE REGISTER

DQB ,DQPB

BYTE

WRITE REGISTER

DQA ,DQPA

BYTE

WRITE REGISTER

ENABLE

REGISTER

Q1

BURST

COUNTER

CLR AND Q0

LOGIC

PIPELINED

ENABLE

DQD ,DQPD

BYTE

WRITE DRIVER

DQC ,DQPC

BYTE

WRITE DRIVER

DQB ,DQPB

BYTE

WRITE DRIVER

DQA ,DQPA

BYTE

WRITE DRIVER

ZZ

SLEEP

CONTROL

MEMORY

ARRAY

SENSE

AMPS

OUTPUT

REGISTERS

OUTPUT

BUFFERS

E

DQs

DQPA

DQPB

DQPC

DQPD

INPUT

REGISTERS

Logic Block Diagram – CY7C1442AV33 (2 Mbit x 18)

A0, A1, A

MODE

ADV

CLK

ADSC

ADSP

BWB

ADDRESS

REGISTER

2 A[1:0]

BURST Q1

COUNTER AND

LOGIC

CLR

Q0

DQB,DQPB

WRITE REGISTER

DQB,DQPB

WRITE DRIVER

DQA,DQPA

BWA

WRITE REGISTER

BWE

DQA,DQPA

WRITE DRIVER

GW

CE1

CE2

ENABLE

REGISTER

PIPELINED

ENABLE

CE3

OE

MEMORY

ARRAY

SENSE

OUTPUT

AMPS

REGISTERS

OUTPUT

BUFFERS

DQs

DQPA

E

DQPB

INPUT

REGISTERS

ZZ

SLEEP

CONTROL

Document #: 38-05383 Rev. *B

Page 2 of 27

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