SST65P542R View Datasheet(PDF) - Silicon Storage Technology
Part Name
Description
Manufacturer
SST65P542R Datasheet PDF : 41 Pages
| |||
Data Sheet
Core Timer Counter Register (CTCR)
Location
7
6
5
0009H
CTD7
CTD6
CTD5
4
CTD4
3
CTD3
2
CTD2
Remote Controller MCU
SST65P542R
1
CTD1
0
CTD0
Reset Value
00H
Symbol
CTD[7:0]
Function
The core timer counter register bit 0 to bit 7. This is a read only status register in which contains
the current value of the 8-bit ripple counter. This counter is clocked by the CPU clock (E/4) and
can be used for various functions, including a software input capture. Extended time can be
achieved by using the timer overflow function to increment a variable to simulate a 16-bit
counter.
SuperFlash Function Register (SFFR)
Location
7
6
5
4
3
2
1
0
Reset Value
000BH PREN MEREN SEREN
-
PROG MERA SERA
-
00H
Symbol
Function
PREN
Byte program enable bit.
0: Disable the byte program.
1: Enable the byte program.
MEREN
Mass (chip) program enable.
0: Disable the mass (chip) erase or program.
1: Enable the mass (chip) erase or program.
SEREN
Sector program enable.
0: Disable the sector erase or program.
1: Enable the sector erase or program.
PROG
Byte program control bit.
0: Not performs the byte program
1: Performs the byte program.
MERA
Mass (chip) program active bit.
0: Not performs the chip program
1: Performs the chip program.
SERA
Sector program active bit.
0: Not performs the sector program.
1: Performs the sector program.
Therefore, when SFFR=22H, the MCU will perform the Sector-Erase, SFFR=44H, the MCU will perform the Chip-
Erase, and SFFR=88H, the MCU will perform the Byte-Program. For a detailed explanation of MCU flash control,
please refer to Section 5.1, “In-Application Programming” on page 21.
©2005 Silicon Storage Technology, Inc.
14
S71170-06-000
7/05
Share Link: 