2048-bits Serial Electrically Erasable PROM
Timing Diagram (3)
CS
ATC
AM93LC56
tCS
SK
**
DI
1
00 0
1
X- - - - - - - - - - - -X DN
DO
tSV
DO
TRI-STATE
BUSY
**AN-2~A0 don't care.
tWP
FIGURE 7. WRITE ALL(WRALL) CYCLE TIMING
READY
tCS
CS
SK
DI
DO
CS
111
AN
AO
TRI-STATE
tSV
tDF
BUSY READY
tWP
FIGURE 8. ERASE(ERASE) CYCLE TIMING
tCS
SK
**
1 0 0 1 0 X- - - - - - - - - X
DI
tSV
tDF
TRI-STATE
DO
BUSY
READY
**AN-2~A0 don't care.
tWP
FIGURE 9. ERASE ALL(ERALL) CYCLE TIMING
Anachip Corp.
www.anachip.com.tw
Rev. A1 Oct 20, 2003
8/10