LTC2232 View Datasheet(PDF) - Linear Technology
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Description
Manufacturer
LTC2232 Datasheet PDF : 28 Pages
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LTC2232/LTC2233
APPLICATIO S I FOR ATIO
The lower limit of the LTC2232/LTC2233 sample rate is
determined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum operat-
ing frequency for the LTC2232/LTC2233 is 1Msps.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits and the overflow bit.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V Range) OF
D9 – D0
(Offset Binary)
>+1.000000V 1
+0.998047V 0
+0.996094V 0
11 1111 1111
11 1111 1111
11 1111 1110
+0.001953V 0
0.000000V 0
–0.001953V 0
–0.003906V 0
10 0000 0001
10 0000 0000
01 1111 1111
01 1111 1110
–0.998047V 0
–1.000000V 0
<–1.000000V 1
00 0000 0001
00 0000 0000
00 0000 0000
D9 – D0
(2’s Complement)
01 1111 1111
01 1111 1111
01 1111 1110
00 0000 0001
00 0000 0000
11 1111 1111
11 1111 1110
10 0000 0001
10 0000 0000
10 0000 0000
VTHRESHOLD = 1.6V
ENC+
1.6V ENC–
0.1µF
LTC2232/
LTC2233
22323 F12a
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
3.3V
MC100LVELT22 3.3V 130Ω
Q0
D0
130Ω
ENC+
Q0
83Ω
ENC–
83Ω
LTC2232/
LTC2233
22323 F12b
Digital Output Buffers
Figure 13 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, iso-
lated from the ADC power and ground. The additional N-
channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2232/LTC2233 should drive a
minimal capacitive load to avoid possible interaction be-
tween the digital outputs and sensitive input circuitry. The
output should be buffered with a device such as an
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
LTC2232/LTC2233
OVDD 0.5V
VDD
VDD
TO 3.6V
0.1µF
DATA
FROM
LATCH
PREDRIVER
LOGIC
OE
OVDD
43Ω
TYPICAL
DATA
OUTPUT
OGND
22323 F13
Figure 13. Digital Output Buffer
Figure 12b. ENC Drive Using a CMOS to PECL Translator
22323fa
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