SDRAM (Rev.0.2)
Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V64S30ATP-8, -10, -12
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Read Interrupted by Precharge @BL=4 CL=3
CLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
/RAS
/CAS
tRRD
tRCD
tRP
tRCD
/WE
CKE
DQM
A0-8
DQM read latency=2
X
XY
Y
X
Y
A10
X
X
X
A9,11
X
X
X
BA0,1
0
10
1 01
1
1
DQ
Q0 Q0 Q0 Q0 Q1 Q1
ACT#0
READ#0
ACT#1
PRE#0
READ#1
PRE#1
ACT#1
READ#1
Burst Read is not interrupted
by Precharge of the other bank.
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
41