PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD9744
(MSB) DB13 1
28 CLOCK
DB12 2
27 DVDD
DB11 3
26 DCOM
DB10 4
25 MODE
DB9
DB8
DB7
5
24 AVDD
6 AD9744 23 RESERVED
TOP VIEW
7 (Not to Scale) 22 IOUTA
DB6 8
21 IOUTB
DB5 9
20 ACOM
DB4 10
19 NC
DB3 11
18 FS ADJ
DB2 12
17 REFIO
DB1 13
16 REFLO
(LSB) DB0 14
15 SLEEP
NC = NO CONNECT
Figure 3. 28-Lead SOIC and TSSOP
DB7 1
DB6 2
DVDD 3
DB5 4
DB4 5
DB3 6
DB2 7
DB1 8
PIN 1
INDICATOR
AD9744
TOP VIEW
(Not to Scale)
24 FS ADJ
23 REFIO
22 ACOM
21 IOUTA
20 IOUTB
19 ACOM
18 AVDD
17 AVDD
NC = NO CONNECT
Figure 4. 32-Lead LFCSP
Table 5. Pin Function Descriptions
SOIC/TSSOP
Pin No.
LFCSP
Pin No.
Mnemonic
1
27
DB13
2 to 13
28 to 32, DB12 to
1, 2, 4 to 8 DB1
14
9
DB0
15
25
SLEEP
16
N/A
REFLO
17
23
REFIO
18
24
FS ADJ
19
N/A
NC
20
19, 22
ACOM
21
20
IOUTB
22
21
IOUTA
23
N/A
RESERVED
24
17, 18
AVDD
25
16
MODE
N/A
15
CMODE
26
10, 26
DCOM
27
3
DVDD
28
N/A
CLOCK
N/A
12
CLK+
N/A
13
CLK−
N/A
11
CLKVDD
N/A
14
CLKCOM
Description
Most Significant Data Bit (MSB).
Data Bits 12 to 1.
Least Significant Data Bit (LSB).
Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left
unterminated if not used.
Reference Ground when Internal 1.2 V Reference Used. Connect to ACOM for both internal
and external reference operation modes.
Reference Input/Output. Serves as reference input when using external reference. Serves as
1.2 V reference output when using internal reference. Requires 0.1 µF capacitor to ACOM
when using internal reference.
Full-Scale Current Output Adjust.
No Internal Connection.
Analog Common.
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
DAC Current Output. Full-scale current when all data bits are 1s.
Reserved. Do not connect to common or supply.
Analog Supply Voltage (3.3 V).
Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement.
Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and
float CLK−). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations
on-chip).
Digital Common.
Digital Supply Voltage (3.3 V).
Clock Input. Data latched on positive edge of clock.
Differential Clock Input.
Differential Clock Input.
Clock Supply Voltage (3.3 V).
Clock Common.
Rev. B | Page 7 of 32