A610 Ver la hoja de datos (PDF) - Intel

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A610

PENTIUM® PROCESSOR at iCOMP® INDEX 61075 MHz

Intel 

PENTIUM® PROCESSOR (610\75)

Symbol

INIT

INTR / LINT0

INV

KEN#

LINT0/INTR

LINT1/NMI

LOCK#

M/IO#

Type

I

I

I

I

I

I

O

O

Table 3. Quick Pin Reference (Contd.)

Name and Function

The Pentium processor (610\75) initialization input pin forces the Pentium

processor (610\75) to begin execution in a known state. The processor state

after INIT is the same as the state after RESET except that the internal caches,

write buffers, and floating point registers retain the values they had prior to

INIT. INIT may NOT be used in lieu of RESET after power up.

If INIT is sampled high when RESET transitions from high to low, the Pentium

processor (610\75) will perform built-in self test prior to the start of program

execution.

An active maskable interrupt input indicates that an external interrupt has

been generated. If the IF bit in the EFLAGS register is set, the Pentium

processor (610\75) will generate two locked interrupt acknowledge bus cycles

and vector to an interrupt handler after the current instruction execution is

completed. INTR must remain active until the first interrupt acknowledge cycle

is generated to assure that the interrupt is recognized.

If the local APIC is enabled, this pin becomes local interrupt 0 .

The invalidation input determines the final cache line state (S or I) in case of

an inquire cycle hit. It is sampled together with the address for the inquire

cycle in the clock EADS# is sampled active.

The cache enable pin is used to determine whether the current cycle is

cacheable or not and is consequently used to determine cycle length. When the

Pentium processor (610\75) generates a cycle that can be cached (CACHE#

asserted) and KEN# is active, the cycle will be transformed into a burst line fill

cycle.

If the APIC is enabled, this pin is local interrupt 0 . If the APIC is disabled, this

pin is interrupt.

If the APIC is enabled, this pin is local interrupt 1 . If the APIC is disabled, this

pin is non-maskable interrupt .

The bus lock pin indicates that the current bus cycle is locked. The Pentium

processor (610\75) will not allow a bus hold when LOCK# is asserted (but

AHOLD and BOFF# are allowed). LOCK# goes active in the first clock of the

first locked bus cycle and goes inactive after the BRDY# is returned for the last

locked bus cycle. LOCK# is guaranteed to be de-asserted for at least one

clock between back-to-back locked cycles.

The memory/input-output is one of the primary bus cycle definition pins. It is

driven valid in the same clock as the ADS# signal is asserted. M/IO#

distinguishes between memory and I/O cycles.

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