LC74401E, 74402, 74402E
Register Data Overview
Address
Symbol
Description
SBY
Standby mode (PLL circuit operating)
STL
Static image (All writing stopped)
NT/PAL
Format selection (high: NTSC, low: PAL)
01
MUL
Multi-mode
FILD
Field display selection
FRM
Frame memory processing selection
P-NUM1, 0
Number of screen B screens displayed (one to four screens)
WRT2 to 0
Dynamic image setting (write screen specification)
D-FIX
Memory clear (fixes the memory write data)
02
POUT-B, A
Sub-screen display on/off
FVP, FHP
Four corner fixed position (screen A) specification
03
VP7 to 0
Screen B vertical position data
04
HP7 to 0
Screen B horizontal position data
FRM-B, A
D/A converter frame on/off
05
FRC-B, A
D/A converter frame color register value specification
YFC5 to 2
D/A converter frame color (Y)
RFC5 to 2
D/A converter frame color (R-Y)
06
BFC5 to 2
D/A converter frame color (B-Y)
VDF-CO
Vertical filter coefficient specification
HDF (horizontal filter on/off when SIZE-H = 1)
HDF, 2E
2E mode (horizontal 2x expansion) on/off when SIZE-H = 0
07
CL-AJ1, 0
A/D converter clamping position adjustment
FM-AJ1, 0
D/A converter frame left/right thickness adjustment
YC-AJ1, 0
Position adjustment for C (R-Y, B-Y) with respect to Y
SIZE-V
Vertical reduction specification H: 1/4 L: 1/3
SIZE-H
Horizontal reduction specification H: 1/6 L: 1/3
08
SPLIT
Split mode (Doubles the number of screens by splitting the sub-screens horizontally.)
PLL7 to 3
PLL divisor value (10011 is the standard value)
WPE-B, A
Wipe or display area function enable
09
TOP to DIA
Wipe or display area function shape specification
WP-MOD
Wipe or display area function selection (high: wipe)
PHP-M, S
Inversion or non-inversion of the field determination result
0A
VBS5 to 0
Display area value setting (vertical direction)
DT-AJ1, 0
Memory control signal (DT) adjustment
0B
HBS5 to 0
Display area value setting (horizontal direction)
TEXT
Partial display of an image reduced 1/2 in the vertical direction
UPPER
Section specification for partial display in TEXT mode
0C
M-BLUE
Blue specification in masking mode
M-LVL
Y level specification for the masked section
YL-5 to 2
Masking level (data compared to the Y level)
WV-AJ1, 0
Write vertical direction adjustment
WH-AJ1, 0
Write horizontal direction adjustment
0D
VP-AJ1, 0
Display position vertical direction adjustment
HP-AJ1, 0
Display position horizontal direction adjustment
0E
DAC1-7 to 0
0F
DAC2-7 to 0
10
DAC3-7 to 0
External control D/A converter (8-bit PWM) data
11
DAC4-7 to 0
12
DAC5-7 to 0
13
DAC6-7 to 0
14
PORT-4 to 1
General-purpose port data
15
V-1/2
Vertical reduction specification 1/2
Note: The register functions at register addresses 0E to 14 can only be used with the LC74401E.
No. 4872-11/19