AD9853AS Ver la hoja de datos (PDF) - Analog Devices
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AD9853AS Datasheet PDF : 31 Pages
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AD9853–SPECIFICATIONS (VS = +3.3 V ؎ 5%, RSET = 3.9 k⍀, Reference Clock Frequency = 20.48 MHz with
6؋ REFCLK Enabled, Symbol Rate = 2.56 MS/s, ␣ = 0.25, unless otherwise noted)
Parameter
Temp Test Level Min Typ Max Units
REF CLOCK INPUT CHARACTERISTICS
Frequency Range
6× REFCLK Disabled (+3.3 V Supply)
6× REFCLK Enabled (+3.3 V Supply)
6× REFCLK Disabled (+5 V Supply)
6× REFCLK Enabled (+5 V Supply)
Duty Cycle
Input Capacitance
Input Impedance
Full
IV
Full
IV
Full
IV
Full
IV
+25°C IV
+25°C V
+25°C V
42
126
7
21
108
168
18
28
40
60
3
100
MHz
MHz
MHz
MHz
%
pF
MΩ
DAC OUTPUT CHARACTERISTICS
Resolution
10
Bits
Full-Scale Output Current
+25°C IV
5
10 20
mA
Gain Error
+25°C I
–10
+10 % FS
Output Offset
+25°C I
10
µA
Output Offset Temperature Coefficient
Full
V
50
nA/°C
Differential Nonlinearity
+25°C I
0.5 0.75 LSB
Integral Nonlinearity
+25°C I
0.5 1.5
LSB
OBSOLETE Output Capacitance
Phase Noise @ 1 kHz Offset, 40 MHz AOUT
6× REFCLK Enabled
6× REFCLK Disabled
Voltage Compliance Range
Wideband SFDR (Single Tone):
1 MHz AOUT
20 MHz AOUT
42 MHz AOUT
65 MHz AOUT1
MODULATOR CHARACTERISTICS
I/Q Offset
Adjacent Channel Power
Error Vector Magnitude
In-Band Spurious Emission
5 MHz–42 MHz AOUT
5 MHz–65 MHz AOUT1
+25°C V
+25°C V
+25°C V
+25°C I
+25°C IV
+25°C IV
+25°C IV
+25°C IV
+25°C IV
+25°C IV
+25°C IV
+25°C IV
+25°C IV
5
pF
–100
dBc
–110
dBc
–0.5
+1.5 V
62 68
dBc
52 54
dBc
48 50
dBc
42 44
dBc
48
44
1
2
42
40
dB
dBm
%
dBc
dBc
Passband Amplitude Ripple
+25°C V
± 0.3
dB
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency
Full
IV
Minimum Clock Pulsewidth Low (tPWL)
Minimum Clock Pulsewidth High (tPWH)
Maximum Clock Rise/Fall Time
Full
IV
Full
IV
Full
IV
Minimum Data Setup Time (tDS)
Minimum Data Hold Time (tDH)
Minimum Clock Setup—Stop Condition (tCS)
Minimum Clock Hold—Start Condition (tCH)
RESET
Full
IV
Full
IV
Full
IV
Full
IV
Minimum TXENABLE Low to RESET Low (tTR)
Minimum RESET High to Start Condition (tRH)
FEC ENABLE
Full
IV
Full
IV
Minimum FEC ENABLE/DISABLE to TXENABLE High (tFH) Full
IV
Minimum FEC ENABLE/DISABLE to TXENABLE Low (tFL) Full
IV
25
MHz
10
ns
10
ns
100
ns
10
ns
10
ns
10
ns
10
ns
10
ns
10
ns
0
ns
0
ns
–2–
REV. C
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