ST72652C4T1 Ver la hoja de datos (PDF) - STMicroelectronics
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componentes Descripción
Fabricante
ST72652C4T1
STMicroelectronics
ST72652C4T1 Datasheet PDF : 166 Pages
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ST7265x
16 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Revision
Main changes
Added TQFP48 and SO34 packages
Changed device summary
Changed section 4.4 on page 22: “and the device can be reprogrammed” added
Added Section 4.7 “Related Documentation” on page 24
Changed section 7 on page 41: removed reference to EICR register (ISx bits are in the
MISCR1 and MISCR3 registers and not in the EICR register).
Changed section 9.1 on page 49: added an important note
Changed section 9.2.4 on page 53: removed references to a second solution when using bit
manipulation
Changed section 9.4 on page 54: modified description of D[7:0] bits
Added text specifying that the watchdog counter is a free-running downcounter: Section
11.1.2 and section 11.1.3 on page 58
Added the following tables: “FLASH Register Map and Reset Values” on page 24, “Miscel-
laneous Register Map and Reset Values” on page 57 and “16-Bit Timer Register Map and
2.3 Reset Values” on page 91
Added Section 11.3.5 and section 11.3.6 on page 70
Removed reference to PWM mode and One Pulse mode in the description of OLVL2 and
OCIE bits in section 11.4.6 on page 88
Updated section 11.6.5.4 on page 104 (removed reference to multimaster system)
Removed reference to BUSY flag in section 11.7.2 on page 109
Removed reference to BUSY bit and BERR bit in Table 34, “I2C Register Map,” on page 117
Added Section 11.7.5 and section 11.7.6 on page 113
Changed section 13.3.1 on page 130 and Figure 74
Changed section 13.7.1 on page 137 and added section 13.7.2 on page 138
Changed section 14 on page 156
Updated description of option byte 0 (section 15.1 on page 159)
Changed section 15.2 on page 160 and section 15.3 on page 162
Date
June 03
Please read carefully Section 9 I/O PORTS
165/166
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