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UDA1324TS

Ultra low-voltage stereo filter DAC

Philips Electronics 

Philips Semiconductors

Ultra low-voltage stereo filter DAC

Preliminary specification

UDA1324TS

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX. UNIT

Digital inputs: pins BCK, WS, DATAI, SYSCLK, APPL0, APPL1, APPL2 and APPL3

VIH

HIGH-level input voltage

VIL

LOW-level input voltage

ILI

input leakage current

CI

input capacitance

0.8VDDD −

−

−

−

−

−

−

Three-level input: pin APPSEL

VIH

HIGH-level input voltage

VIM

MIDDLE-level input voltage

VIL

LOW-level input voltage

0.8VDDD −

0.3VDDD −

−0.5

−

DAC

−

V

0.2VDDD V

1

µA

10

pF

VDDD + 0.5 V

0.7VDDD V

0.2VDDD V

Vref(DAC)

Io(max)

RO

RL

CL

reference voltage

maximum output current

output resistance

load resistance

load capacitance

referenced to VSSA

(THD + N)/S < 0.1%;

RL = 5 kΩ

note 2

0.45VDDA 0.5VDDA

−

0.16

−

0.15

3

−

−

−

0.55VDDA V

−

mA

2.0

Ω

−

kΩ

50

pF

Notes

1. All supply connections must be made to the same external power supply unit.

2. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent

oscillations in the output operational amplifier.

AC CHARACTERISTICS

VDDD = VDDA = 2.0 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ; all voltages referenced to ground (pins VSSA and VSSD);

unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX. UNIT

DAC

Vo(rms)

output voltage (RMS value)

−

∆Vo

unbalance voltage between

−

channels

(THD + N)/S total harmonic

distortion-plus-noise to

signal ratio

at 0 dB

−

at −60 dB; A-weighted −

S/N

αcs

PSRR

signal-to-noise ratio

code = 0; A-weighted −

channel separation

−

power supply ripple rejection fripple = 1 kHz;

−

ratio

Vripple = 100 mV (p-p)

500

−

mV

0.1

−

dB

−83

−78

dB

−36

−

dB

97

−

dB

100

−

dB

50

−

dB

2000 Jan 20

12

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