ASAHI KASEI
[AK5370]
Digital DC Characteristics
Ta=0 - 70°C; VD=3.0 - 3.6V; DGND=0V Measurement under static state
All digital pins except DP, DN. Schmitt hysteresis level of RST pin and levels of all test pins will not be tested.
Parameter
Symbol
Min
Typ
Max
Units
AGCE pin H level input voltage
VIH
70%VA
V
AGCE pin L level input voltage
VIL
30%VA
V
RSTN pin H level voltage
VIHR
2.0
V
RSTN pin L level voltage
VILR
0.8
V
H level output voltage
IOH= 2mA
VOH
2.4
V
L level output voltage
IOL= -2mA
VOL
0.6
V
Input Leakage Current
Iin
±10
µA
Ta=25°C, VA=VD=3.3V
Parameter
Master Clock Frequency
Reset input width @RSTN pin(low active)
Singe Ended Receiver Threshold
Switching Characteristics
Symbol
Min
MCLK
-
Wrst
1.0
Vse
0.8
Typ
11.2896
Max
-
2.0
Units
MHz
us
V
Main Clock Stable Time
Tostb
100
ms
Vse(max) of D+ to stabilized MCLK
( Xtal oscillator start up + PLL lock -in )
Reset Signal Recognition
Both D+ and D- < Vse(min) to Reset mode
Trst_rec
2.5
5.5
µs
Device Ready
Tdrr
10
ms
Ready for transaction after reset
Suspend Recognition
Tsus_rec
3.0
ms
Idle state ( D+ > Vse(max) & D - < Vse(min) )
to Suspend mode
Resume Time
Tresm
30
ms
First flip of D+/D- from Idle sate
To Device Ready*)
Device Ready: VREF, Xtal oscillator, and PLL get stable and bus trans action with normal rate is ready.
VD
D+
D- "L"
RST
Master
Clock
Tostb
Reset Mode
Device
Connected
Trst_rec
Tdrr
Reset Mode
Figure 1. Mode change with respect to BUS States 1 (Power on and device connected)
MS0027-E-00
5
2000/05