P83C880 Ver la hoja de datos (PDF) - Unspecified

Número de pieza

componentes Descripción

Fabricante

P83C880

Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.

Unspecified 

Philips Semiconductors

Microcontrollers for monitors with DDC

interface, auto-sync detection and sync proc.

Product specification

P83Cx80; P87C380

9 WATCHDOG TIMER

In addition to the standard timers, a Watchdog Timer

consisting of an 10-bit prescaler and an 8-bit timer is also

incorporated. The timer is increased every 19.5 ms for an

oscillator frequency of 16 MHz; this is derived from the

oscillator frequency (fclk) by the formula:

ftimer = 3----0---4-----f×--c--l-k1---0----2---4--

When a timer overflow occurs, the microcontroller is reset.

To prevent a system reset, the timer must be reloaded

before an overflows occurs, by the application software.

If the processor suffers a hardware/software malfunction,

the software will fail to reload the timer. This failure will

produce a reset upon overflow thus preventing the

processor running out of control.

The Watchdog Timer can only be reloaded if the condition

flag WLE (PCON.4) has been previously set by software.

At the moment the counter is loaded the condition flag is

automatically cleared.

In the Idle mode the Watchdog Timer and reset circuitry

remain active.

The time interval between timer reloading and the

occurrence of a reset, depends on the reloaded value.

The Watchdog Timer’s time interval is:

t = t1 × --(--2---5--1--6-0---2-–---4-T----2---)--

Where T2 = decimal value of the T2 register contents and

t1 = 15.2 µs (fclk = 10 MHz); t1 = 12.7 µs (fclk = 12 MHz)

and t1 = 19 µs (fclk = 16 MHz).

For example, this may range from 19.5 ms to 5.0 s when

using an oscillator frequency of 16 MHz.

Table 27 lists the resolution and the maximum time interval

of the Watchdog Timer using different system clocks.

The Watchdog Timer is controlled by the Watchdog control

bits:

• EW2; DFCON.7 (SFR address C0H)

• EW1; PWM10H.7 (SFR address C6H)

• EW0; PWM10L.7 (SFR address C6H).

Only when EW2 to EW0 = 101 the Watchdog Timer is

disabled and allows the Power-down mode to be enabled.

The rest of pattern combinations will keep the Watchdog

Timer enabled and disable the Power-down mode.

This security key with multiple flags split in two SFRs will

prevent the Watchdog Timer from being terminated

abnormally when the function of the Watchdog Timer is

needed.

Table 27 Resolution and the maximum time interval of the WDT

fclk

(MHz)

10

12

16

PRESCALER FACTOR

152

304

RESOLUTION

(ms)

15.56

12.97

19.46

MAXIMUM TIME INTERVAL

(s)

4.0

3.3

5.0

1997 Dec 12

21

Share Link: