EVAL-AD7687SDZ(RevC) Ver la hoja de datos (PDF) - Analog Devices
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EVAL-AD7687SDZ
(Rev.:RevC)
(Rev.:RevC)
Analog Devices
EVAL-AD7687SDZ Datasheet PDF : 28 Pages
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Data Sheet
insensitive to power supply variations over a wide frequency
range, as shown in Figure 32, which represents PSRR over
frequency.
100
95
VDD = 5V
90
85
80
75
VDD = 2.5V
70
65
60
55
50
1
10
100
1000
10000
FREQUENCY (kHz)
Figure 32. PSRR vs. Frequency
The AD7687 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 33. This makes the part
ideal for low sampling rate (even a few Hz) and low battery-
powered applications.
1000
10
0.1
VDD = 5V
VDD = 2.5V
VIO
0.001
10
100
1000
10000
100000
SAMPLING RATE (SPS)
Figure 33. Operating Currents vs. Sampling Rate
1000000
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7687, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 34. The reference line can be driven by either
The system power supply directly.
A reference voltage with enough current output capability,
such as the ADR43x.
A reference buffer, such as the AD8031, which can also
filter the system power supply, as shown in Figure 34.
AD7687
5V 10k
1F
5V
5V
10
AD8031 10F
1F
1
REF
VDD
VIO
AD7687
1OPTIONAL REFERENCE BUFFER AND FILTER.
Figure 34. Example of Application Circuit
DIGITAL INTERFACE
Though the AD7687 has a reduced number of pins, it offers
flexibility in its serial interface modes.
The AD7687, when in CS mode, is compatible with SPI, QSPI,
digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or
ADSP-219x. This interface can use either 3-wire or 4-wire. A
3-wire interface using the CNV, SCK, and SDO signals
minimizes wiring connections useful, for instance, in isolated
applications. A 4-wire interface using the SDI, CNV, SCK, and
SDO signals allows CNV, which initiates the conversions, to be
independent of the readback timing (SDI). This is useful in low
jitter sampling or simultaneous sampling applications.
The AD7687, when in chain mode, provides a daisy chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is always selected.
In either mode, the AD7687 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a BUSY signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a BUSY indicator,
the user must time out the maximum conversion time prior to
readback.
The BUSY indicator feature is enabled as
In the CS mode, if CNV or SDI is low when the ADC
conversion ends (Figure 38 and Figure 42).
In the chain mode, if SCK is high during the CNV rising
edge (Figure 46).
Rev. C | Page 17 of 28
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