EP1C12T173C6 Ver la hoja de datos (PDF) - Altera Corporation
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EP1C12T173C6 Datasheet PDF : 104 Pages
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Embedded Memory
Independent Clock Mode
The M4K memory blocks implement independent clock mode for true
dual-port memory. In this mode, a separate clock is available for each port
(ports A and B). Clock A controls all registers on the port A side, while
clock B controls all registers on the port B side. Each port, A and B, also
supports independent clock enables and asynchronous clear signals for
port A and B registers. Figure 2–17 shows an M4K memory block in
independent clock mode.
Figure 2–17. Independent Clock Mode
6 LAB Row Clocks
6
dataA[ ]
DQ
ENA
byteenaA[ ]
DQ
ENA
Notes (1), (2)
A
Data In
Memory Block
256 ´ 16 (2)
512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
B
Data In
Byte Enable A
Byte Enable B
QD
ENA
QD
ENA
6
dataB[ ]
byteenaB[ ]
addressA[ ]
wrenA
clkenA
clockA
DQ
ENA
Address A
DQ
ENA
Write
Pulse
Generator
Write/Read
Enable
Data Out
Address B
QD
ENA
Write/Read
Enable
Data Out
Write
Pulse
Generator
QD
ENA
addressB[ ]
wrenB
clkenB
clockB
DQ
ENA
qA[ ] qB[ ]
QD
ENA
Notes to Figure 2–17:
(1) All registers shown have asynchronous clear ports.
(2) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
Input/Output Clock Mode
Input/output clock mode can be implemented for both the true and
simple dual-port memory modes. On each of the two ports, A or B, one
clock controls all registers for inputs into the memory block: data input,
wren, and address. The other clock controls the block's data output
registers. Each memory block port, A or B, also supports independent
clock enables and asynchronous clear signals for input and output
registers. Figures 2–18 and 2–19 show the memory block in input/output
clock mode.
Altera Corporation
January 2007
2–25
Preliminary
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