ADUM1280BRZ-RL7 Ver la hoja de datos (PDF) - Analog Devices

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ADUM1280BRZ-RL7

3 kV RMS Dual Channel Digital Isolators

Analog Devices 

ADuM1280/ADuM1281/ADuM1285/ADuM1286

Data Sheet

APPLICATIONS INFORMATION

PC BOARD LAYOUT

The ADuM1280/ADuM1281/ADuM1285/ADuM1286 digital

isolator requires no external interface circuitry for the logic

interfaces. Power supply bypassing is strongly recommended at

both input and output supply pins VDD1 and VDD2 (see Figure 12).

The capacitor value should be between 0.01 µF and 0.1 µF. The total

lead length between both ends of the capacitor and the input power

supply pin should not exceed 20 mm.

The ADuM1280/ADuM1281/ADuM1285/ADuM1286 can

readily meet CISPR 22 Class A (and FCC Class A) emissions

standards, as well as the more stringent CISPR 22 Class B (and

FCC Class B) standards in an unshielded environment, with

proper PCB design choices. Refer to the AN-1109 Applicaton

Note, Recommendations for Control of Radiated Emissions with

iCoupler Devices for PCB-related EMI mitigation techniques,

including board layout and stack-up issues.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes

a logic signal to propagate through a component. The input-to-

output propagation delay time for a high-to-low transition may

differ from the propagation delay time of a low-to-high transition.

INPUT (VIx)

OUTPUT (VOx)

tPLH

tPHL

50%

50%

Figure 12. Propagation Delay Parameters

Pulse width distortion is the maximum difference between these

two propagation delay values and an indication of how accurately

the timing of the input signal is preserved.

Channel-to-channel matching refers to the maximum amount the

propagation delay differs between channels within a single

ADuM1280/ADuM1281/ADuM1285/ADuM1286 component.

Propagation delay skew refers to the maximum amount the

propagation delay differs between multiple ADuM1280/

ADuM1281/ADuM1285/ADuM1286 components operating

under the same conditions.

DC CORRECTNESS AND MAGNETIC FIELD

IMMUNITY

Positive and negative logic transitions at the isolator input cause

narrow (~1 ns) pulses to be sent via the transformer to the decoder.

The decoder is bistable and is, therefore, either set or reset by

the pulses indicating input logic transitions. In the absence of

logic transitions at the input for more than ~1.6 µs, a periodic

set of refresh pulses indicative of the correct input state are sent to

ensure dc correctness at the output.

If the decoder receives no pulses for more than about 6.4 µs, the

input side is assumed to be unpowered or nonfunctional, in which

case, the isolator output is forced to a default low state by the

watchdog timer circuit.

The limitation on the device’s magnetic field immunity is set by

the condition in which induced voltage in the transformer

receiving coil is sufficiently large to either falsely set or reset the

decoder. The following analysis defines such conditions. The

ADuM1280 is examined in a 3 V operating condition because it

represents the most susceptible mode of operation of this

product.

The pulses at the transformer output have an amplitude greater

than 1.5 V. The decoder has a sensing threshold of about 1.0 V,

therefore establishing a 0.5 V margin in which induced voltages

can be tolerated. The voltage induced across the receiving coil is

given by

V = (−dβ/dt)∑πrn2; n = 1, 2, …, N

where:

β is the magnetic flux density.

rn is the radius of the nth turn in the receiving coil.

N is the number of turns in the receiving coil.

Given the geometry of the receiving coil in the ADuM1280 and an

imposed requirement that the induced voltage be, at most, 50% of

the 0.5 V margin at the decoder, a maximum allowable magnetic

field is calculated, as shown in Figure 13.

100

10

1

0.1

0.01

0.001

1k

10k

100k

1M

10M

MAGNETIC FIELD FREQUENCY (Hz)

100M

Figure 13. Maximum Allowable External Magnetic Flux Density

Rev. C | Page 18 of 22

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