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IGLOO Low Power Flash FPGAs with Flash* Freeze Technology

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IGLOO Low Power Flash FPGAs

Table 2-15 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to Standard I/O Banks

VCCI (V)

Static Power

PDC6 (mW)1

Dynamic Power

PAC9 (µW/MHz)2

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

3.3V LVCMOS Wide Range3

3.3

–

3.3

–

17.24

17.24

2.5 V LVCMOS

2.5

–

5.64

1.8 V LVCMOS

1.8

–

2.63

1.5 V LVCMOS (JESD8-11)

1.5

–

1.97

1.2 V LVCMOS4

1.2

–

0.57

1.2 V LVCMOS Wide Range4

1.2

–

0.57

Notes:

1. PDC6 is the static power (where applicable) measured on VCCI.

2. PAC9 is the total dynamic power measured on VCCI.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

4. Applicable for IGLOO V2 devices only.

Table 2-16 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1

Applicable to Advanced I/O Banks

Single-Ended

CLOAD (pF) VCCI (V)

Static Power

PDC7 (mW)2

Dynamic Power

PAC10 (µW/MHz)3

3.3 V LVTTL / 3.3 V LVCMOS

3.3V LVCMOS Wide Range4

5

3.3

–

5

3.3

–

136.95

136.95

2.5 V LVCMOS

5

2.5

–

76.84

1.8 V LVCMOS

5

1.8

–

49.31

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS5

1.2 V LVCMOS Wide Range5

5

1.5

–

5

1.2

–

5

1.2

–

33.36

16.24

16.24

3.3 V PCI

10

3.3

–

194.05

3.3 V PCI-X

10

3.3

–

194.05

Differential

LVDS

–

2.5

7.74

156.22

LVPECL

–

3.3

19.54

339.35

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

5. Applicable for IGLOO V2 devices only.

Revision 23

2- 11

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