5. Power Sequence
Sequence for power on/off and Signal on/off
Power on
VGH
GND
VCC
Model
Version
Page
: A070FW03 V4
:3
: 8 /20
VGH
Power off
VCC
GND
VCC
T1
T1 T2
VGL
VGL
OFF
T3
Video Signal, Logic Signal
ON
T5 T5
T4 T6
T7
OFF
T1 ≦ 15ms (From 10%*VCC to 90%*VCC,when VCC is Low to High);
T2 ≦ 10ms (From 90%*VCC to 10%*VGH,when VCC is Low to High);
T3 ≦ 10ms (From 90%*VGH to Video signal,when VGH is Low to High);
T4 ≦ 10ms (From Video signal to 90%*VGH,when VGH is High to Low);
T5 ≦ 20ms (From 90%*VCC to 10%*VCC,when VCC is High to Low);
T6 ≦ 10ms (From 10%*VGH to 90%*VCC,when VCC is Low to High);
T7 ≧ 0.4s (From 10%*VCC is H→L to 10%*VCC is L→H)。
ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED,
OR TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM AU OPTRONICS CORP.