RESET LAST
Bits: 14
When a "1" is written to RESET LAST, all the bits in the LAST STATUS REGISTER except the
ADDRESS field and the BUSY bit are set to a "0". The contents of the register are not affected
by this operation and RESET LAST is always read by the host as "0".
SYNUPD
Bits: 12
1= Specifies that the lower 16 bits of the RTC will be updated whenever a valid mode command
"Synchronize With Data" is received by the RT.
*LOCK
Bits: 11
0 = Enables updating of the host output register after the RTC CONTROL register is read (this
feature is needed to support byte wide read cycles).
1 = Enables updating of the host output register after the lower RTC word is read.
SYNRST
Bits: 10
1= Specifies that the RTC shall be reset whenever a valid mode command "Synchronize Without
Data" is received by the RT.
RES
Bits: 13, 9, 8
This field defines the resolution of the RTC in microseconds as follows:
RESOLUTION(us)
13
9
8
1
0
0
0
2
0
0
1
4
0
1
0
8
0
1
1
16
1
0
0
32
1
0
1
64
OFF/EXT
1
1
0
1
1
1
Note: Some NHi- RT device types have an external TIME TAG CLOCK input.
M1760
Bits: 7
1= Specifies that the RT shall comply with MIL- STD- 1760A. This mode of operation has two
consequences: first, the mode command "Synchronize With Data" updates the lower 16 bits
of the RTC only if the least significant data bit is "0" and second, the IPO_ DSC pin serves as
a store disconnect signal rather than an interrupt priority output.
0= Specifies that the RT shall comply with MIL-STD-1553B.
BUSY _OPT
Bits: 6
0= MRST, Software Reset and MODE CODE_ 08 RESET will set the BUSY bit in the LAST
STATUS REGISTER and the BASIC STATUS REGISTER to a "1".
1= Only MRST will set the BUSY bit in the LAST STATUS REGISTER and the BASIC STATUS
REGISTER to a "1".
RESET BUSY
Bits: 5
When a "1" is written to RESET BUSY, the BUSY bit in the LAST STATUS REGISTER is set to
a "0". The contents of the register are not affected by this operation and RESET BUSY is always
read by the host as "0".
- 17 -