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11274-011

Programmable Line Lock Clock Generator IC

AMI Semiconductor 

FS6131-01

Programmable Line Lock Clock Generator IC

The goal is to choose the highest crystal frequency from

Table 10 that generates the smallest value of NR.

The equation establishing the output frequency (fCLK) as a

function of the input VCXO frequency is

f CLK = N F

fVCXO N R

(Eqn. 1)

where NF is the Feedback Divider modulus.

Choose a few different crystal frequencies from Table 10

and factor both the input VCXO and output clock fre-

quencies into prime numbers. Look for the factors that

will give the smallest modulus for NR with the largest

FVCXO. The output and VCXO frequencies and the re-

duced factors from Eqn. 1 are in Table 25.

Table 25: Clock Regenerator Example

VCXO FREQUENCY

FROM Table 10

f CLK

NF

(fVCXO, MHz)

f VCXO

NR

51840000

324

20.00

20000000

125

51840000

8

19.44

19440000

3

25.248

51840000

540

25248000

263

51840000

135

24.576

24576000

64

A 19.44MHz crystal provides the smallest modulus for NR

(NR=3) with the highest crystal frequency.

Finally, choose a Post Divider (NPx) modulus that keeps

the VCO frequency in its most comfortable range. The

VCO frequency (fVCO) can be calculated by

fVCO = f CLK N Px

Selecting an overall modulus of NPx=3 sets the VCO fre-

quency at 155.52MHz when the loop is locked.

15.2 Example Programming

To generate a de-jittered output frequency of 51.84MHz

from an 8kHz reference, program the following (refer to

Figure 33):

• Program the VCXO Control ROM to 3 via

XLROM[2:0] to select an external 19.44MHz crystal

• Enable the VCXO fine tune via XLVTEN=1

• Enable the Crystal Loop PFD via XLPDEN=0 and

XLSWAP=0

• Set the Reference Divider input to select the VCXO

via REFDSRC

• Set the PFD input to select the Reference Divider

and the Feedback Divider via PDREF and PDFBK

• Set the Reference Divider (NR) to a modulus of 3 via

REFDIV[11:0]

• Set the Feedback Divider input to select the VCO via

FBKDSRC

• Set the Feedback Divider (NF) to a modulus of 8 via

FBKDIV[14:0]

• Set NP1=1, NP2=3, and NP3=1 for a combined Post

Divider modulus of NPx=3 via POST1[1:0],

POST2[1:0], and POST3[1:0].

• Select the internal loop filter via EXTLF

• Set VCOSPD=0 to select the VCO high speed range

These settings provide the highest frequency at the Main

Loop Phase Frequency Detector of 6.48MHz. The use of

a 19.44MHz crystal requires that XLROM[2:0] be set to

three as shown in Table 10.

39

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