SSD0817(2002) Ver la hoja de datos (PDF) - Solomon Systech

Número de pieza

componentes Descripción

Fabricante

SSD0817
(Rev.:2002)

LCD Segment / Common Driver with Controller

Solomon Systech  

4. Bias Ratio Selection circuitry

The bias ratios can be software selected from 1/4, 1/5, 1/6, 1/7, 1/8 and 1/9.

Since there will be slightly different in command pattern for different MUX, please refer to Command

Descriptions section for detail description.

5. Self adjust temperature compensation circuitry

This block provides 4 different compensation settings to satisfy various liquid crystal temperature grades

by software control. The default temperature coefficient (TC) setting is TC0.

Oscillator Circuit

This module is an On-Chip low power RC oscillator circuitry (Figure 5). The oscillator generates the clock

for the DC-DC voltage converter. This clock is also used in the Display Timing Generator.

enable

Oscillation Circuit

Oscillator

enable

enable

Buffer

(CL)

Internal resistor

OSC1

OSC2

Figure 5 - On-Chip low power RC oscillator circuitry

Reset Circuit

This block includes Power On Reset (POR) circuitry and the hardware reset pin, RES . The POR and

Hardware reset performs the same reset function. Once RES receives a reset pulse, all internal circuitry

will start to initialize. Minimum pulse width the reset sequence is 1us. Status of the chip after reset is

given by:

Display is turned OFF

Default Display Mode

64 MUX: 104 x 64 + 1 Icon Line

Normal segment and display data column address mapping (Seg0 mapped to Row address 00h)

Read-modify-write mode is OFF

Power control register is set to 000b

Register data clear in I2C-bus interface

Bias ratio is set to default

64 MUX: 1/9

Static indicator is turned OFF

Display start line is set to GDDRAM column 0

Column address counter is set to 00h

Page address is set to 0

Normal scan direction of the COM outputs

Contrast control register is set to 20h

Test mode is turned OFF

Temperature Coefficient is set to TC0

Display Data Latch

This block is a series of latches carrying the display signal information. These latches hold the data,

which will be fed to the HV Buffer Cell and Level Selector to output the required voltage level.

The numbers of latches of different members are given by:

15

SSD0817 Series

Rev 1.0

03/2002

SOLOMON

Share Link: