IDT72V36110L6BBGI Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT72V36110L6BBGI Datasheet PDF : 48 Pages
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
D/Q35
D/Q35
1st Parallel Offset Write/Read Cycle
D/Q19D/Q17
D/Q8
EMPTY OFFSET REGISTER (PAE)
D/Q0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
17 16 15 14 13 12 11 10 9
87 6 5 4321
# of Bits Used
2nd Parallel Offset Write/Read Cycle
D/Q19 D/Q17
D/Q8
FULL OFFSET REGISTER (PAF)
D/Q0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
# of Bits Used
IDT72V36100/IDT72V36110 ⎯ x36 Bus Width
Non-Interspersed
Parity
Interspersed
Parity
Non-Interspersed
Parity
Interspersed
Parity
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
# of Bits Used:
16 bits for the IDT72V36100
17 bits for the IDT72V36110
Note: All unused bits of the
LSB & MSB are don’t care
1st Parallel Offset Write/Read Cycle
D/Q17
D/Q16
Data Inputs/Outputs
EMPTY OFFSET (LSB) REGISTER (PAE)
D/Q0
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
D/Q8
# of Bits Used
Non-Interspersed
Parity
Interspersed
Parity
2nd Parallel Offset Write/Read Cycle
D/Q17
D/Q16
Data Inputs/Outputs
D/Q0
FULL OFFSET (LSB) REGISTER (PAF)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
D/Q8
IDT72V36100 ⎯ x18 Bus Width
1st Parallel Offset Write/Read Cycle
D/Q17
D/Q16
Data Inputs/Outputs
EMPTY OFFSET (LSB) REGISTER (PAE)
D/Q0
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
D/Q8
# of Bits Used
2nd Parallel Offset Write/Read Cycle
D/Q17 D/Q16
Data Inputs/Outputs
EMPTY OFFSET (MSB) REGISTER (PAE)
D/Q0
17
17
Non-Interspersed
Parity
Interspersed
Parity
3rd Parallel Offset Write/Read Cycle
D/Q17
D/Q16
Data Inputs/Outputs
D/Q0
FULL OFFSET (LSB) REGISTER (PAF)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
D/Q8
4th Parallel Offset Write/Read Cycle
D/Q17 D/Q16
Data Inputs/Outputs
FULL OFFSET (MSB) REGISTER (PAF)
D/Q0
17
17
IDT72V36110 ⎯ x18 Bus Width
6117 drw07
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
16
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