IDT72V36110L6BBGI Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT72V36110L6BBGI

3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 36-BIT FIFO

Integrated Device Technology 

IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

65,536 x 36 and 131,072 x 36

tJTCKF

tTCK

tJTCKR

tJTCKL

tJTCKH

TCK

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

TDI/

TMS

TDO

tDS tDH

tJRSR

tDO

TRST(1)

tJRST

NOTE:

1. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.

Figure 31. Standard JTAG Timing

TDO

6117 drw36

SYSTEM INTERFACE PARAMETERS

IDT72V36100

IDT72V36110

Parameter Symbol Test Conditions Min. Max. Units

Data Output

tDO(1)

- 20 ns

Data Output Hold tDOH(1)

0

- ns

Data Input

tDS

tDH

trise=3ns

tfall=3ns

10

- ns

10

-

NOTE:

1. 50pf loading on external output signals.

JTAG AC ELECTRICAL

CHARACTERISTICS

(VCC = 3.3V ± 5%; Tcase = 0°C to +85°C)

Parameter

Symbol Test

Conditions Min. Max. Units

JTAG Clock Input Period tTCK

-

100 - ns

JTAG Clock HIGH

tJTCKH

-

40 - ns

JTAG Clock Low

tJTCKL

-

40 - ns

JTAG Clock Rise Time tJTCKR

-

- 5(1) ns

JTAG Clock Fall Time tJTCKF

-

- 5(1) ns

JTAG Reset

tJRST

-

50 - ns

JTAG Reset Recovery tJRSR

-

50 - ns

NOTE:

1. Guaranteed by design.

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