MAX31850JATB-T Ver la hoja de datos (PDF) - Maxim Integrated
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MAX31850JATB-T Datasheet PDF : 25 Pages
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MAX31850/MAX31851
Cold-Junction Compensated, 1-Wire
Thermocouple-to-Digital Converters
1-Wire TIMING CHARACTERISTICS
(3.0V P VDD P 3.6V, TA = -40NC to +125NC, unless otherwise noted.) (Notes 2, 3)
PARAMETER
Time to Strong Pullup On
Time Slot
Recovery Time
Write-0 Low Time
Write-1 Low Time
Read Data Valid
Reset Time High
Reset Time Low
Presence Detect High
Presence Detect Low
Capacitance: DQ
Capacitance: AD0–AD3
SYMBOL
tSPON
tSLOT
tREC
tLOW0
tLOW1
tRDV
tRSTH
tRSTL
tPDHIGH
tPDLOW
CIN/OUT
CIN_ADD
CONDITIONS
Start Convert T command issued
(Note 15)
(Note 15)
(Note 15)
(Note 15)
(Note 15)
(Note 15)
(Notes 15, 16)
(Note 15)
(Note 15)
(Note 17)
(Note 17)
MIN TYP MAX UNITS
8
µs
60
120
µs
1
µs
60
120
µs
1
15
µs
15
µs
480
µs
480
µs
15
60
µs
60
240
µs
25
pF
50
pF
Note 2: Limits are 100% production tested at TA = +25NC. Limits over the operating temperature range and relevant supply volt-
age range are guaranteed by design and characterization.
Note 3: Limits are 100% production tested at TA = +25NC and +85NC. Limits over the operating temperature range and relevant sup-
ply voltage are guaranteed by design and characterization.
Note 4: All voltages are referenced to GND. Currents entering the IC are specified positive and currents exiting the IC are negative.
Note 5: The pullup supply voltage specification assumes that the pullup device is ideal, and therefore the high level of the pullup
Note 6:
is equal to VPU. To meet the device’s VIH specification, the actual supply rail for the strong pullup transistor must include
margin for the voltage drop across the transistor when it is turned on. Thus: VPU_ACTUAL = VPU_IDEAL + VTRANSISTOR.
To guarantee a presence pulse under low-voltage parasite power conditions, VILMAX, may have to be reduced to as low
as 0.5V.
Note 7: Standby current specified up to +70NC.
Note 8: To minimize IDDS, DQ should be within the following ranges: VGND P VDQ P VGND + 0.3V or VDD - 0.3V P VDQ P VDD.
Note 9: Active current refers to supply current during active temperature conversions.
Note 10: DQ is high (high-impedance state with external pullup).
Note 11: Not including cold-junction temperature error or thermocouple nonlinearity.
Note 12: Guaranteed by design. These limits represent six sigma distribution for TA = +25NC to +85NC. Outside this temperature
range, these limits are three sigma distribution.
Note 13: Guaranteed by design. These limits represent a three sigma distribution.
Note 14: After minimum VDD has been reached during power-up, wait 10ms before initiating temperature conversions.
Note 15: See the 1-Wire Timing Diagrams.
Note 16: Under parasite power, if tRSTL > 960Fs, a power-on reset (POR) may occur.
Note 17: Represents the maximum capacitive load that may be applied to the pins and still maintain timing and logic state.
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