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MAX5133A

+5V/+3V, 13-Bit, Serial, Force/Sense DACs with 10ppm/°C Internal Reference

Maxim Integrated 

+5V/+3V, 13-Bit, Serial, Force/Sense DACs

with 10ppm/°C Internal Reference

Table 3. Detailed SSPCON Register Contents

CONTROL BIT

WCOL

SSPOV

BIT7

BIT6

SSPEN

BIT5

CKP

SSPM3

SSPM2

SSPM1

SSPM0

X = Don’t care

BIT4

BIT3

BIT2

BIT1

BIT0

MAX5132/MAX5133

SETTINGS

X

X

1

0

0

0

0

1

SYNCHRONOUS SERIAL-PORT CONTROL REGISTER

(SSPCON)

Write-Collision Detection Bit

Receive-Overflow Detection Bit

Synchronous Serial Port Enable Bit

0: Disables serial port and configures these pins as I/O port pins.

1: Enables serial port and configures SCK, SDO, and SCI as seri-

al-port pins.

Clock-Polarity Select Bit. CKP = 0 for SPI master-mode selection.

Synchronous Serial-Port Mode Select Bit. Sets SPI master mode

and selects fCLK = fOSC / 16.

Table 4. Detailed SSPSTAT Register Contents

CONTROL BIT

SMP

BIT7

CKE

D/A

P

S

R/W

UA

BF

X = Don’t care

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

MAX5132/MAX5133

SETTINGS

0

1

X

X

X

X

X

X

SYNCHRONOUS SERIAL-PORT STATUS REGISTER

(SSPSTAT)

SPI Data-Input Sample Phase. Input data is sampled at the mid-

dle of the data-output time.

SPI Clock-Edge Select Bit. Data will be transmitted on the rising

edge of the serial clock.

Data-Address Bit

Stop Bit

Start Bit

Read/Write Bit Information

Update Address

Buffer Full-Status Bit

__________Applications Information

Definitions

Integral Nonlinearity (INL)

Integral nonlinearity (Figure 8a) is the deviation of the

values on an actual transfer function from a straight

line. This straight line can be either a best-straight-line

fit (closest approximation to the actual transfer curve) or

a line drawn between the endpoints of the transfer func-

tion, once offset and gain errors have been nullified. For

a DAC, the deviations are measured at every single

step.

Differential Nonlinearity (DNL)

Differential nonlinearity (Figure 8b) is the difference

between an actual step height and the ideal value of

1LSB. If the magnitude of the DNL is less than or equal to

1LSB, the DAC guarantees no missing codes and is

monotonic.

Offset Error

The offset error (Figure 8c) is the difference between

the ideal and the actual offset point. For a DAC, the off-

set point is the step value when the digital input is zero.

This error affects all codes by the same amount and

can usually be compensated for by trimming.

14 ______________________________________________________________________________________

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