MAX8650(2006) Ver la hoja de datos (PDF) - Maxim Integrated

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MAX8650
(Rev.:2006)

4.5V to 28V Input Current-Mode Step-Down Controller with Adjustable Frequency

Maxim Integrated 

4.5V to 28V Input Current-Mode Step-Down

Controller with Adjustable Frequency

Applications Information

PC Board Layout Guidelines

Careful PC board layout is critical to achieve low switch-

ing losses and clean, stable operation. The switching

power stage requires particular attention. Follow these

guidelines for good PC board layout:

1) Place IC decoupling capacitors as close to IC pins

as possible. Keep the power ground plane and sig-

nal ground plane separate. Place the input ceramic

decoupling capacitor directly across and as close as

possible to the high-side MOSFET’s drain and the

low-side MOSFET’s source. This is to help contain

the high switching current within this small loop.

2) For output current greater than 10A, a multilayer PC

board is recommended. Pour a signal ground plane

in the second layer underneath the IC to minimize

noise coupling.

3) Connect input, output, and VL capacitors to the

power ground plane; connect all other capacitors to

the signal ground plane.

4) Place the inductor current-sense resistor and capac-

itor as close to the inductor as possible. Make a

Kelvin connection to minimize the effect of PC board

trace resistance. Place the input-bias balance resis-

tor (R5 in Figures 8 and 9) near CS-. Run two closely

parallel traces from across the capacitor (C9 in

Figures 8 and 9) to CS+ and CS-.

5) Place the MOSFET as close as possible to the IC to

minimize trace inductance of the gate-drive loop. If

parallel MOSFETs are used, keep the trace lengths

to both gates equal.

6) Connect the drain leads of the power MOSFET to a

large copper area to help cool the device. Refer to

the power MOSFET data sheet for recommended

copper area.

7) Place the feedback and compensation components

as close to the IC pins as possible. Connect the

feedback resistor-divider from FB to the output as

close as possible to the farthest output capacitor.

8) Refer to the MAX8650 evaluation kit for an example

layout.

Chip Information

PROCESS: BiCMOS

Pin Configuration

TOP VIEW

FSYNC 1

MODE 2

SYNCO 3

BST 4

DH 5

LX 6

DL 7

PGND 8

VL 9

IN 10

EN 11

AVL 12

MAX8650

QSOP

24 POK

23 SCOMP

22 ILIM2

21 REFIN

20 SS

19 COMP

18 FB

17 OVP

16 ILIM1

15 CS-

14 CS+

13 GND

24 ______________________________________________________________________________________

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