MAX9526(2010) Ver la hoja de datos (PDF) - Maxim Integrated
Número de pieza
componentes Descripción
Fabricante
MAX9526 Datasheet PDF : 38 Pages
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Low-Power, High-Performance
NTSC/PAL Video Decoder
Table 1. MAX9526 Clock Mode Summary
SEL
_54MHz
REGISTER 0x0D
B4
XTAL_DIS
REGISTER 0x0D
B3
PLLBYP
REGISTER 0x0E
B3
LLC_MODE
REGISTER 0x0E
B5-4
CLOCK MODE DESCRIPTION
Input clock = 27MHz crystal.
0
0
0
00
Sample clock = line locked or async (autodetected).
This is the default power-up mode for the MAX9526.
0
0
0
10
Input clock = 27MHz crystal.
Sample clock = line locked (forced on).
0
0
0
11
Input clock = 27MHz crystal.
Sample clock = 2x input clock.
Invalid modes. The PLL can only be bypassed if the
0
X
1
XX
input clock is 54MHz.
0
1
0
00
Input clock = 27MHz external clock.
Sample clock = line locked or async (autodetected).
0
1
0
10
Input clock = 27MHz external clock.
Sample clock = line locked (forced on).
0
1
0
11
Input clock = 27MHz external clock.
Sample clock = 2x input clock.
1
0
X
XX
Invalid mode. 54MHz crystal not supported.
1
1
0
00
Input clock = 54MHz external clock.
Sample clock = line locked or async (autodetected).
1
1
0
10
Input clock = 54MHz external clock.
Sample clock = line locked (forced on).
Input clock = 54MHz external clock.
1
1
0
11
Sample clock = input clock divided by 2, then
multiplied by 2x through the PLL. This mode uses the
PLL to filter high-frequency jitter on the input source.
1
1
1
X0
Invalid mode. The PLL can only be bypassed when
the output is not a line-locked clock.
Input clock = 54MHz external clock.
1
1
1
11
Sample clock = input clock. Use this mode when a
low-jitter, 54MHz input clock is used.
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