MAX9526AEI/V-T(2010) Ver la hoja de datos (PDF) - Maxim Integrated

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MAX9526AEI/V-T
(Rev.:2010)

Low-Power, High-Performance NTSC/PAL Video Decoder

Maxim Integrated 

Low-Power, High-Performance

NTSC/PAL Video Decoder

Video Input Select and Clamp Control Register

REG

B7

B6

B5

B4

B3

0x09

AUTOSEL

INSEL

DCRESTORE_RANGE

0

B2

B1

B0

0

D_CLMP_DIS

0

Video Auto-Select (AUTOSEL)

1 = Automatically selects video input with activity

detect.

When activity is present on both or neither VIN1 and

VIN2 after a reset (POR, register reset, sleep mode,

shutdown), VIN1 is selected. If there is activity on VIN2

and no activity on VIN1, then VIN2 is selected. When

VIN2 is automatically selected with the presence of

activity, the input switches to VIN1 only when activity

goes away on VIN2.

0 = Video input is selected manually (default).

See INSEL (register 0x09, B6) for manual input selection.

Manual Video Input Select (INSEL)

1 = Select VIN2.

0 = Select VIN1 (default).

Video autoselect bit (AUTOSEL) must be 0 for this reg-

ister to take effect.

Analog DC Restoration Current Range

(DCRESTORE_RANGE)

This bit sets the full-scale range of the DC restoration

DAC. Increasing the full-scale current range increases

the bandwidth and range of the DC restoration loop.

10 = Slow (±3µA into video input coupling capacitor)

11 = Medium (±6µA into video input coupling capacitor)

00 = Medium-fast (±12µA into video input coupling

capacitor) (default)

01 = Fast (±24µA into video input coupling capacitor)

Digital Clamp Disable (D_CLMP_DIS)

This bit disables the digital clamp.

1 = Disables digital sync-tip clamp (default).

0 = Enables digital sync-tip clamp.

Enabling the digital clamp sets the sync level to code 0

(decimal) and gives higher frequency tracking of input

signals. If the digital clamp is enabled, the sync slice

level in register 0x0F should be adjusted accordingly to

provide equivalent noise rejection. Typically,

SSLICE[3:0] should be reduced by 2 LSBs when

D_CLMP_DIS is set to 1.

Gain-Control Register

REG

B7

B6

B5

B4

B3

B2

B1

B0

0x0A

CRAGC

CMPAGC

0

ADAGC

AGCGAIN

Chrominance AGC Disable (CRAGC)

1 = Chroma gain is frozen.

0 = Automatic chroma gain is based on color burst

level (default).

To freeze the chroma gain at the default value of 17

(hex), set CRAGC = 1 and apply a soft reset.

Composite AGC Disable (CMPAGC)

1 = Digital composite gain frozen at default value

(80 (hex)).

0 = Automatic digital composite gain based on sync

level (default).

Disable Analog Automatic Gain Control (ADAGC)

1 = Analog automatic gain control is disabled.

0 = Analog automatic gain control is enabled (default).

The analog automatic gain-control (AGC) loop adjusts

the AGC gain to optimally use the available ADC full-

scale range.

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