MT48LC4M32B2P Ver la hoja de datos (PDF) - Micron Technology

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MT48LC4M32B2P

1 Meg x 32 x 4 Banks SDR SDRAM

Micron Technology 

128Mb: x32 SDRAM

Features

List of Figures

Figure 1: 4 Meg x 32 Functional Block Diagram ................................................................................................. 8

Figure 2: 86-Pin TSOP Pin Assignments (Top View) ........................................................................................... 9

Figure 3: 90-Ball FBGA Ball Assignments (Top View) ....................................................................................... 10

Figure 4: 86-Pin Plastic TSOP II (400 mil) – Package Codes TG/P ...................................................................... 12

Figure 5: 90-Ball VFBGA (8mm x 13mm) ......................................................................................................... 13

Figure 6: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ................................................. 15

Figure 7: Example: Temperature Test Point Location, 90-Ball VFBGA (Top View) .............................................. 16

Figure 8: ACTIVE Command .......................................................................................................................... 25

Figure 9: READ Command ............................................................................................................................. 26

Figure 10: WRITE Command ......................................................................................................................... 27

Figure 11: PRECHARGE Command ................................................................................................................ 28

Figure 12: Initialize and Load Mode Register .................................................................................................. 36

Figure 13: Mode Register Definition ............................................................................................................... 38

Figure 14: CAS Latency .................................................................................................................................. 41

Figure 15: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 .......................................................... 42

Figure 16: Consecutive READ Bursts .............................................................................................................. 44

Figure 17: Random READ Accesses ................................................................................................................ 45

Figure 18: READ-to-WRITE ............................................................................................................................ 46

Figure 19: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 47

Figure 20: READ-to-PRECHARGE .................................................................................................................. 47

Figure 21: Terminating a READ Burst ............................................................................................................. 48

Figure 22: Alternating Bank Read Accesses ..................................................................................................... 49

Figure 23: READ Continuous Page Burst ......................................................................................................... 50

Figure 24: READ – DQM Operation ................................................................................................................ 51

Figure 25: WRITE Burst ................................................................................................................................. 52

Figure 26: WRITE-to-WRITE .......................................................................................................................... 53

Figure 27: Random WRITE Cycles .................................................................................................................. 54

Figure 28: WRITE-to-READ ............................................................................................................................ 54

Figure 29: WRITE-to-PRECHARGE ................................................................................................................. 55

Figure 30: Terminating a WRITE Burst ............................................................................................................ 56

Figure 31: Alternating Bank Write Accesses ..................................................................................................... 57

Figure 32: WRITE – Continuous Page Burst ..................................................................................................... 58

Figure 33: WRITE – DQM Operation ............................................................................................................... 59

Figure 34: READ With Auto Precharge Interrupted by a READ ......................................................................... 61

Figure 35: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 62

Figure 36: READ With Auto Precharge ............................................................................................................ 63

Figure 37: READ Without Auto Precharge ....................................................................................................... 64

Figure 38: Single READ With Auto Precharge .................................................................................................. 65

Figure 39: Single READ Without Auto Precharge ............................................................................................. 66

Figure 40: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 67

Figure 41: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 67

Figure 42: WRITE With Auto Precharge ........................................................................................................... 68

Figure 43: WRITE Without Auto Precharge ..................................................................................................... 69

Figure 44: Single WRITE With Auto Precharge ................................................................................................. 70

Figure 45: Single WRITE Without Auto Precharge ............................................................................................ 71

Figure 46: Auto Refresh Mode ........................................................................................................................ 73

Figure 47: Self Refresh Mode .......................................................................................................................... 75

Figure 48: Power-Down Mode ........................................................................................................................ 76

Figure 49: Clock Suspend During WRITE Burst ............................................................................................... 77

Figure 50: Clock Suspend During READ Burst ................................................................................................. 78

PDF: 09005aef80872800

128mb_x32_sdram.pdf - Rev. U 04/13 EN

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