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UPD784038GK-XXX-BE9

78K/IV Series 16-bit single-chip microcomputer

NEC => Renesas Technology 

APPENDIX C REVISION HISTORY

Revisions through this document are listed in the following table. The column "Applicable Chapters" indicates

the chapters in each edition.

(1/3)

Edition

2nd edition

3rd edition

Major Revisions from Previous Edition

• The following instructions are added to bit manipulation instructions.

MOV1 CY, !addr16.bit

CY, !!addr24, bit

!addr16.bit, CY

!!addr24.bit, CY

AND1, OR1

CY, !addr16.bit

CY, !!addr24.bit

CY,/!addr16.bit

CY,/!!addr24.bit

XOR1 CY, !addr16.bit

CY,!!addr24.bit

NOT1, SET1, CLR1

!addr16.bit

!!addr24.bit

• The following instructions are added to conditional branch instructions.

BF, BT, BFSET, BTCLR

!addr16.bit, $addr20

!!addr24.bit, $addr20

• Descriptions regarding µPD784915 Subseries are added.

• µPD784020 is added to µPD784026 Subseries.

Notation used in section 5.2.10 Short direct 24-bit memory indirect

addressing changed as follows: [%saddrp] → [%saddrg]

• saddrg1 and saddrg2 are added to section 6.1 Legend, (1) Operand

Identifiers and Description (2/2).

• MOVG operand corrected as follows:

[TDE+HL], WHL → [TDE+C], WHL

• Section 6.5 Number of Instruction Clocks is added

• 3.5-inch 2HC or 3.5-inch 2HD is added as supply medium for IBM PC/AT

• Part numbers for ordering integrated debuggers are changed as follows:

µS5A10ID78K4 → µSAA10ID78K4

µS5A13ID78K4 → µSAA13ID78K4

µS7B10ID78K4 → µSBB10ID78K4

Applicable Chapters

CHAPTER 6

INSTRUCTION SET

Throughout

CHAPTER 5 ADDRESSING

CHAPTER 6

INSTRUCTION SET

CHAPTER 8

DEVELOPMENT TOOLS

486

User’s Manual U10905EJ8V1UM

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