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Fabricante

TQ2059

High-Frequency Clock Generator

TriQuint Semiconductor 

TQ2059

AC Characteristics (VDD = +5 V + 5%, TA = 0 °C to +70 °C)

Symbol

tCPWH

tCPWL

tIR

Input Clock (REFCLK)

CLK pulse width HIGH

CLK pulse width LOW

Input rise time

(0.8 V – 2.0 V)

Test Conditions

Figure 2

Figure 2

Min

Typ

Max

Unit

4

—

—

ns

4

—

—

ns

—

—

2.0

ns

Symbol

tOR, tOF

tCYC

tJP2

tSYNC3

Input Clock (REFCLK)

Rise/fall time (20% – 80%)

Duty-cycle

Period-to-Period Jitter

Synchronization Time

Test Conditions

Figure 2

Figure 2

Min

Typ

Max

Unit

100

220

350

ps

45

50

55

%

—

30

120

ps

—

10

500

µs

Notes: 1. All measurements are tested with a REFCLK having a rise time of 0.5 ns (0.8 V to 2.0 V).

2. Jitter specification is peak to peak. Period-to-Period jitter is the jitter on the output with respect to the output's previous crossing.

3. tSYNC is the time required for the PLL to synchronize and assumes the presence of a CLK signal.

Figure 1

Figure 2

4

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