MAX8661(2006) Ver la hoja de datos (PDF) - Maxim Integrated

Número de pieza

componentes Descripción

Fabricante

MAX8661
(Rev.:2006)

High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications

Maxim Integrated 

High-Efficiency, Low-IQ, PMICs with Dynamic

Voltage Management for Mobile Applications

Power-Up and Power-Down Timing

Figure 6 shows the power-up sequence for the Intel

XScale family of processors. In general, the supplies

should power up in the following order:

1) POWER-UP: V8 V5 V1 and V2 V3 and V4

2) REG6 and REG7 typically power external card slots

and can be powered up and down based on appli-

cation requirements.

Note that the Intel XScale processor controls

EN1/EN2/EN5 with the same SYS_EN signal, yet Intel’s

timing diagrams show that V5 is supposed to power up

before V1 and V2. Because of the Intel XScale family’s

timing parameters, most systems connect EN1/EN2/

EN5 together and drive them with SYS_EN. When pow-

ering up, this connection ensures that V5 powers up

before V1 and V2 (only when V5 is powered from IN).

Intel XScale Power Configuration Register (PCFR)

The MAX8660/MAX8661 comply with the Intel XScale

power I2C register specifications. This allows the PMIC

to be used along with the Intel XScale processor with

little-to-no software development. As shown in Table 9,

there are many I2C registers, but since the Intel XScale

processor automatically updates the PMIC through its

power I2C interface, only the REG6 and REG7 enable

bits need be programmed to fully utilize the PMIC.

V8

(VCC_BBATT)

RSO

(nRESET)

LBO

(nBATT_FAULT)

EN1/EN2/EN5

(SYS_EN)

V5

(VCC_MVT)

V1

(VCC_IO)

V2

(VCC_MEM)

EN34

(PWR_EN)

tVBHRSTH = 20ms, MIN (TIMED BY PMIC)

tVBHBFH = 0s, MIN (TIMED BY PMIC)

tBFHSEH = 93.75μs, MAX (TIMED BY XScale)

tBSTHSEH = 2.05s, MAX (TIMED BY XScale)

tSEHVMH = SYS_DEL TIME, MAX (TIMED BY PMIC)

tVMHVSH1 = SYS_DEL TIME, tSEHVMH, MAX (TIMED BY PMIC)

tVMHVSH2 = SYS_DEL TIME - t, tSEHVMH, MAX (TIMED BY PMIC)

tSEHPH = SYS_DEL TIME + 152μs, MIN

tSEHPH = SYS_DEL TIME + 153μs, MAX (TIMED BY XScale)

SCL FROM XScale

(PWR_SCL)

SCA FROM XScale

(PWR_SDA)

nRESET_OUT*

FROM XScale

V3

(VCC_APPS)

tSHROH = SYS_DEL TIME +213μs, MIN

tSHROH = SYS_DEL TIME +214μs, MAX (TIMED BY XScale)

tPHLVTH3 = PWR_DEL TIME (TIMED BY PMIC)

V4

(VCC_SRAM)

tPHLVTH4 = PWR_DEL TIME (TIMED BY PMIC)

*THE MAX8660/MAX8661 DO NOT DIRECTLY USE THE INTEL XScale PROCESSOR’S nRESET_OUT LOGIC OUTPUT.

Figure 6. Power-Up Timing

______________________________________________________________________________________ 31

Share Link: